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DS21352 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21352
Beschreibung 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS21352 Datasheet, Funktion
www.maxim-ic.com
3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
FEATURES
§ Complete DS1/ISDN–PRI/J1 transceiver functionality
§ Long and Short haul LIU
§ Crystal–less jitter attenuator
§ Generates DSX–1 and CSU line build-outs
§ HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
§ Dual two–frame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
§ 8.192MHz clock output locked to RCLK
§ Interleaving PCM Bus Operation
§ Per-channel loopback and idle code insertion
§ 8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive functionality
§ Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
§ IEEE 1149.1 JTAG-Boundary Scan
§ Pin compatible with DS2152/54/354/554 SCTs
§ 100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
PIN ASSIGNMENT
DS21352
DS21552
100
1
ORDERING INFORMATION
DS21352L
DS21352LN
DS21552L
DS21552LN
(0°C to +70°C)
(-40°C to +85°C)
(0°C to +70°C)
(-40°C to +85°C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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DS21352 Datasheet, Funktion
2. LIST OF TABLES
DS21352/DS21552
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11
Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14
Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29
Table 6-1 DEVICE ID BIT MAP .............................................................................................................33
Table 6-2 OUTPUT PIN TEST MODES .................................................................................................36
Table 7-1 RECEIVE T1 LEVEL INDICATION .....................................................................................47
Table 7-2 ALARM CRITERIA ................................................................................................................49
Table 8-1 LINE CODE VIOLATION COUNTING ARRANGEMENTS ..............................................53
Table 8-2 PATH CODE VIOLATION COUNTING ARRANGEMENTS.............................................54
Table 8-3 MULTIFRAMES OUT OF SYNC COUNTING ARRANGMENTS .....................................55
Table 14-1 ELASTIC STORE DELAY AFTER INITIALIZATION......................................................67
Table 14-2 MINIMUM DELAY MODE CONFIGURATION................................................................67
Table 15-1 TRANSMIT HDLC CONFIGURATION...............................................................................68
Table 15-2 HDLC/BOC CONTROLLER REGISTERS ..........................................................................70
Table 16-1 LINE BUILD OUT SELECT IN LICR .................................................................................86
Table16-2 TRANSMIT TRANSFORMER SELECTION .......................................................................87
Table 16-3 TRANSFORMER SPECIFICATIONS..................................................................................88
Table 16-4 PULSE TEMPLATE CORNER POINTS..............................................................................90
Table 16-5 RECEIVE MONITOR MODE GAIN....................................................................................95
Table 17-1 TRANSMIT CODE LENGTH...............................................................................................97
Table 17-2 RECEIVE CODE LENGTH ..................................................................................................97
Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE .......................................104
Table 19-2 ID CODE STRUCTURE .....................................................................................................105
Table 19-3 DEVICE ID CODES ............................................................................................................105
Table 19-4 BOUNDARY SCAN CONTROL BITS ..............................................................................106
Table 20-1 MASTER DEVICE BUS SELECT.....................................................................................110
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6 Page









DS21352 pdf, datenblatt
DS21352/DS21552
50
TDATA
I Transmit Data
51
TSYSCLK
I Transmit System Clock
52
TSSYNC
I Transmit System Sync
53
TCHCLK
O Transmit Channel Clock
54 CO O Carry Out
55
MUX
I Bus Operation
56
D0/AD0
I/O Data Bus Bit0/ Address/Data Bus Bit 0
57
D1/AD1
I/O Data Bus Bit1/ Address/Data Bus Bit 1
58
D2/AD2
I/O Data Bus Bit 2/Address/Data Bus 2
59
D3/AD3
I/O Data Bus Bit 3/Address/Data Bus Bit 3
60
DVSS
– Digital Signal Ground
61
DVDD
- Digital Positive Supply
62
D4/AD4
I/O Data Bus Bit4/Address/Data Bus Bit 4
63
D5/AD5
I/O Data Bus Bit 5/Address/Data Bus Bit 5
64
D6/AD6
I/O Data Bus Bit 6/Address/Data Bus Bit 6
65
D7/AD7
I/O Data Bus Bit 7/Address/Data Bus Bit 7
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73
ALE (AS)/A7
I Address Latch Enable/Address Bus Bit 7
74
RD*(DS*)
I Read Input(Data Strobe)
75 CS* I Chip Select
76
FMS
I Framer Mode Select
77
WR*(R/W*)
I Write Input(Read/Write)
78
RLINK
O Receive Link Data
79
RLCLK
O Receive Link Clock
80
DVSS
– Digital Signal Ground
81
DVDD
– Digital Positive Supply
82
RCLK
O Receive Clock
83
DVDD
– Digital Positive Supply
84
DVSS
– Digital Signal Ground
85
RDATA
O Receive Data
86
RPOSI
I Receive Positive Data Input
87
RNEGI
I Receive Negative Data Input
88
RCLKI
I Receive Clock Input
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER (cont.)
PIN
SYMBOL
TYPE DESCRIPTION
89
RCLKO
O Receive Clock Output
90
RNEGO
O Receive Negative Data Output
91
RPOSO
O Receive Positive Data Output
92
RCHCLK
O Receive Channel Clock
93
RSIGF
O Receive Signaling Freeze Output
94
RSIG
O Receive Signaling Output
95
RSER
O Receive Serial Data
96
RMSYNC
O Receive Multiframe Sync
97
RFSYNC
O Receive Frame Sync
98
RSYNC
I/O Receive Sync
99
RLOS/LOTC
O Receive Loss Of Sync/ Loss Of Transmit Clock
100 RSYSCLK I Receive System Clock
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12 Page





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