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DS21348GN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21348GN
Beschreibung 3.3V E1/T1/J1 Line Interface
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS21348GN Datasheet, Funktion
www.maxim-ic.com
FEATURES
§ Complete E1, T1, or J1 line interface unit
(LIU)
§ Supports both long-haul and short-haul
trunks
§ Internal software-selectable receive-side
termination for 75/100/120W
§ 3.3V power supply
§ 32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
§ Generates the appropriate line build-outs,
with and without return loss, for E1 and
DSX-1 and CSU line build-outs for T1
§ AMI, HDB3, and B8ZS, encoding/decoding
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered clock
§ Programmable monitor mode for receiver
§ Loopbacks and PRBS pattern generation/
detection with output for received errors
§ Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
§ 8-bit parallel or serial interface with optional
hardware mode
§ Muxed and nonmuxed parallel bus supports
Intel or Motorola
§ Detects/generates blue (AIS) alarms
§ NRZ/bipolar interface for TX/RX data I/O
§ Transmit open-circuit detection
§ Receive Carrier Loss (RCL) indication
(G.775)
§ High-Z State for TTIP and TRING
§ 50mA (rms) current limiter
DS21348/Q348
3.3V E1/T1/J1 Line Interface
PIN DESCRIPTION
44
1
44 TQFP
7 mm
CABGA
ORDERING INFORMATION
DS21348TN 44-Pin TQFP (-40°C to +85°C)
DS21348T 44-Pin TQFP (0o C to +70oC)
DS21348GN 7mm CABGA (-40°C to +85°C)
DS21348G 7mm CABGA (0o C to +70oC)
DS21Q348N (Quad) BGA (-40°C to +85°C)
DS21Q348 (Quad) BGA (0o C to +70o C)
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DS21348GN Datasheet, Funktion
DS21348/Q348
3. INTRODUCTION
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use
internal termination, software selectable for 75/100/120W applications, or external termination. The
device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348
contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in
transmission. The receive circuitry is also configurable for various monitor applications. The device has a
usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and
TNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348
will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long haul (CSU) or short haul (DSX-1) lines for T1.
3.1 DOCUMENT REVISION HISTORY
1) Datasheet for 3.3V only, 011801.
2) Added supply current measurements; added thermal characteristics of quad package, 092101.
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DS21348GN pdf, datenblatt
ACRONYM
RCLK
RD*
(DS*)
RCL/
LOTC
PIN
40
2
25
RNEG
39
RPOS
38
RTIP/
RRING
TCLK
27/
28
43
TEST
TNEG
TPOS
TTIP/
TRING
VDD
VSM
VSS
26
42
41
34/
37
21/
36
20
22/
35
I/O DESCRIPTION
DS21348/Q348
O Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
I Read Input (Data Strobe). RD* and DS* are active low signals.
DS active low when in nonmultiplexed, Motorola mode. See the Bus
Timing Diagrams in Section 12.
O Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 msec ± 2
msec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
O Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 8.4 for details.
O Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
I Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
I Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 3-3.
I 3-State Control. Set high to 3-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
I Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
I Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
O Transmit Tip and Ring [TTIP & TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 7 for details.
- Positive Supply. 5.0V ±5%
I Voltage Supply Mode. Should be tied high for 5V operation.
- Signal Ground.
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