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EPM7064AE Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPM7064AE
Beschreibung Programmable Logic Device
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EPM7064AE Datasheet, Funktion
October 2002, ver. 4.3
Includes
® MAX 7000AE
MAX 7000A
Programmable Logic
Device
Data Sheet
Features...
f
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
Altera Corporation
DS-M7000A-4.3
1






EPM7064AE Datasheet, Funktion
MAX 7000A Programmable Logic Device Data Sheet
Functional
Description
The MAX 7000A architecture includes the following elements:
Logic array blocks (LABs)
Macrocells
Expander product terms (shareable and parallel)
Programmable interconnect array
I/O control blocks
The MAX 7000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 7000A devices.
6 Altera Corporation

6 Page









EPM7064AE pdf, datenblatt
MAX 7000A Programmable Logic Device Data Sheet
Figure 4. MAX 7000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From
Previous
Macrocell
Product-
Term
Select
Matrix
Preset
Clock
Clear
Macrocell
Product-
Term Logic
36 Signals 16 Shared
from PIA Expanders
Product-
Term
Select
Matrix
Preset
Clock
Clear
Macrocell
Product-
Term Logic
To Next
Macrocell
Programmable Interconnect Array
Logic is routed between LABs on the PIA. This global bus is a
programmable path that connects any signal source to any destination on
the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell
outputs feed the PIA, which makes the signals available throughout the
entire device. Only the signals required by each LAB are actually routed
from the PIA into the LAB. Figure 5 shows how the PIA signals are routed
into the LAB. An EEPROM cell controls one input to a 2-input AND gate,
which selects a PIA signal to drive into the LAB.
12 Altera Corporation

12 Page





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