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EP7312-CV-C Schematic ( PDF Datasheet ) - ETC

Teilenummer EP7312-CV-C
Beschreibung HIGH-PERFORMANCE/ LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
Hersteller ETC
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Gesamt 64 Seiten
EP7312-CV-C Datasheet, Funktion
www.DataSheet4U.com
EP7312 Data Sheet
FEATURES
I ARM®720T Processor
— ARM7TDMI CPU operating at speeds of 74 and 90
MHz
— 8 KBytes of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
I Ultra low power
— 90 mW at 74 MHz typical
— 108 mW at 90 MHz typical
— <.03 mW in the Standby State
I Advanced audio decoder/decompression capability
— Supports bit streams with adaptive bit rates
— Allows for support of multiple audio
decompression algorithms (MP3, WMA, AAC,
Audible, etc.)
High-Performance,
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
OVERVIEW
The Cirrus LogicEP7312 is designed for ultra-low-
power portable and line-powered applications such as
portable consumer entertainment devices, home and car
audio juke box systems, and general purpose industrial
control applications, or any device that features the
added capability of digital audio compression &
decompression. The core-logic functionality of the device
is built around an ARM720T processor with 8 KBytes of
four-way set-associative unified cache and a write buffer.
Incorporated into the ARM720T is an enhanced memory
management unit (MMU) which allows for support of
sophisticated operating systems like Microsoft®
Windows® CE and Linux®.
BLOCK DIAGRAM
(cont.)
(cont.)
D ig ita l
A u d io
In terfa ce
S erial
In terfa ce
Power
M an ag em ent
(2) UARTs
w/ IrDA
Boot
ROM
Internal Data Bus
EPB Bus
ARM720T
IC E -J T A G
ARM7TDMI CPU Core
8 KB
Cache
W rite
B u ffe r
MMU
Bus
Bridge
M averickKeyTM
M em ory Controller
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
Clocks &
Tim ers
In terru p ts ,
P W M & G P IO
Keypad&
Touch
S creen I/F
LCD
C o n tro lle r
http://www.cirrus.com
MEMORY and STORAGE
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
Nov ’03
DS508PP5






EP7312-CV-C Datasheet, Funktion
EP7312
High-Performance, Low-Power System on Chip
Description of the EP7312’s Components, Functionality, and Interfaces
The following sections describe the EP7312 in more
detail.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro
controller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Entries
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7312 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7312 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
Memory Interfaces
Power Management
The EP7312 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V. The device has three basic
power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
Table 1 shows the power management pin assignments.
Table 1. Power Management Pin Assignments
There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density. shows the Static Memory Interface
pin assignments.
Table 2. Static Memory Interface Pin Assignments
Pin Mnemonic
I/O Pin Description
Pin Mnemonic
BATOK
nEXTPWR
I/O Pin Description
I Battery ok input
I
External power supply sense
input
nCS[5:0]
A[27:0]
D[31:0]
nMOE/nSDCAS
(Note)
O Chip select out
O Address output
I/O Data I/O
O ROM expansion OP enable
nPWRFL
I Power fail sense input
nMWE/nSDWE
(Note) O ROM expansion write enable
nBATCHG
I Battery changed sense input
HALFWORD
O
Halfword access select
output
MaverickKeyUnique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
WORD
WRITE/nSDRAS
(Note)
O Word access select output
O Transfer direction
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
©6 Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5

6 Page









EP7312-CV-C pdf, datenblatt
EP7312
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated
EP7312 completes a low-power system solution. All
necessary interface logic is integrated on-chip.
CRYSTAL
CRYSTAL
×16
SDRAM
×16
SDRAM
×16
SDRAM
×16
SDRAM
×16
FLASH
×16
FLASH
×16
FLASH
×16
FLASH
EXTERNAL MEMORY-
MAPPED EXPANSION
BUFFERS
ADDITIONAL I/O
BUFFERS
AND
LATCHES
MOSCIN
RTCIN
D[0-31]
A[0-27]
nMOE
WRITE
SDRAS/
SDCAS
SDCS[0]
SDQM[0-3]
SDCS[1]
SDQM[0-3]
nCS[0]
nCS[1]
CS[n]
WORD
nCS[2]
nCS[3]
LEDFLSH
DD[0-3]
CL1
CL2
FRM
M
COL[0-7]
PA[0-7]
PB[0-7]
PD[0-7]
PE[0-2]
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
DRIVE[0-1]
FB[0-1]
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
LEDDRV
PHDIN
RXD[[1/2]
TXD[1/2]
DSR
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
LCD
KEYBOARD
POWER
SUPPLY UNIT
AND
COMPARATORS
DC
INPUT
BATTERY
DC-TO-DC
CONVERTERS
CODEC/SSI2/
DAI
IR LED AND
PHOTODIODE
2× RS-232
TRANSCEIVERS
ADC
DIGITIZER
Figure 1. A Fully-Configured EP7312-Based System
Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.
©12 Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5

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