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EN29F040-55PI Schematic ( PDF Datasheet ) - ETC

Teilenummer EN29F040-55PI
Beschreibung 4 Megabit (512K x 8-bit) Flash Memory
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
EN29F040-55PI Datasheet, Funktion
EN29F040
4 Megabit (512K x 8-bit) Flash Memory
EN29F040
FEATURES
5.0V operation for read/write/erase
operations
Fast Read Access Time
- 45ns, 55ns, 70ns, and 90ns
Sector Architecture:
- 8 uniform sectors of 64Kbytes each
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within
individual sectors
High performance program/erase speed
- Byte program time: 10µs typical
- Sector erase time: 500ms typical
- Chip erase time: 3.5s typical
Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
Low Power Active Current
- 30mA active read current
- 30mA program/erase current
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle
bits feature
Single Sector and Chip Erase
Sector Unprotect Mode
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
0.35 µm double-metal double-poly
triple-well CMOS Flash Technology
Low Vcc write inhibit < 3.2V
100K endurance cycle
Package Options
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
Commercial and Industrial Temperature
Ranges
GENERAL DESCRIPTION
The EN29F040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized
into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of
64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040 features 5.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT
states in high-performance microprocessor systems.
The EN29F040 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E )
controls, which eliminate bus contention issues. This device is designed to allow either single (or
multiple) Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev. D, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685






EN29F040-55PI Datasheet, Funktion
USER MODE DEFINITIONS
EN29F040
Standby Mode
The EN29F040 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).
It is placed in CMOS-compatible standby when the CE pin is at VCC ± 0.5. The device also has a
TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is placed in
TTL-compatible standby when the CE pin is at VIH. When in standby modes, the outputs are in a
high-impedance state independent of the OE input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See “Reset Command” section.
See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more
information. The Read Operations table provides the read parameters, and Read Operation Timings
diagram shows the timing diagram.
Output Disable Mode
When the OE pin is at a logic high level (VIH), the output from the EN29F040 is disabled. The
output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on
address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage
Method) table. In addition, when verifying sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The
Command Definitions table shows the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
VID. See “Command Definitions” for details on using the autoselect mode.
4800 Great America Parkway, Suite 202
6
Santa Clara, CA 95054
Rev. D, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

6 Page









EN29F040-55PI pdf, datenblatt
EN29F040
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read
mode without changing data in all protected sectors.
Toggling either CE or OE will cause DQ6 to toggle.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5 Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” (The Toggle Bit (DQ6) should also be checked at this
time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.) This is a
failure condition that indicates the program or erase cycle was not successfully completed. . DATA
Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition. Setting
the CE to VIH will partially power down the device under those conditions.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return the device to reading
array data.
DQ2 Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when
the system reads at addresses within those sectors that have been selected for erasure. (The system may
use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and
DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See
also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
4800 Great America Parkway, Suite 202
12
Santa Clara, CA 95054
Rev. D, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685

12 Page





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