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376 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer 376
Beschreibung 376TM HIGH PERFORMANCE 32-BIT EMBEDDED PROCESSOR
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 70 Seiten
376 Datasheet, Funktion
376TM HIGH PERFORMANCE
32-BIT EMBEDDED PROCESSOR
Y Full 32-Bit Internal Architecture
8- 16- 32-Bit Data Types
8 General Purpose 32-Bit Registers
Extensive 32-Bit Instruction Set
Y High Performance 16-Bit Data Bus
16 or 20 MHz CPU Clock
Two-Clock Bus Cycles
16 Mbytes Sec Bus Bandwidth
Y 16 Mbyte Physical Memory Size
Y High Speed Numerics Support with the
80387SX
Y Low System Cost with the 82370
Integrated System Peripheral
Y On-Chip Debugging Support Including
Break Point Registers
Y Complete Intel Development Support
C PL M Assembler
ICETM-376 In-Circuit Emulator
iRMK Real Time Kernel
iSDM Debug Monitor
DOS Based Debug
Y Extensive Third-Party Support
Languages C Pascal FORTRAN
BASIC and ADA
Hosts VMS UNIX MS-DOS and
Others
Real-Time Kernels
Y High Speed CHMOS IV Technology
Y Available in 100 Pin Plastic Quad Flat-
Pack Package and 88-Pin Pin Grid Array
(See Packaging Outlines and Dimensions 231369)
INTRODUCTION
The 376 32-bit embedded processor is designed for high performance embedded systems It provides the
performance benefits of a highly pipelined 32-bit internal architecture with the low system cost associated with
16-bit hardware systems The 80376 processor is based on the 80386 and offers a high degree of compatibil-
ity with the 80386 All 80386 32-bit programs not dependent on paging can be executed on the 80376 and all
80376 programs can be executed on the 80386 All 32-bit 80386 language translators can be used for
software development With proper support software any 80386-based computer can be used to develop and
test 80376 programs In addition any 80386-based PC-AT compatible computer can be used for hardware
prototyping for designs based on the 80376 and its companion product the 82370
80376 Microarchitecture
240182 – 48
Intel iRMK ICE 376 386 Intel386 iSDM Intel1376 are trademarks of Intel Corp
UNIX is a registered trademark of AT T
ADA is a registered trademark of the U S Government Ada Joint Program Office
PC-AT is a registered trademark of IBM Corporation
VMS is a trademark of Digital Equipment Corporation
MS-DOS is a trademark of MicroSoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1990
Order Number 240182-004






376 Datasheet, Funktion
376 EMBEDDED PROCESSOR
Symbol
HLDA
INTR
NMI
BUSY
ERROR
PEREQ
FLT
NC
VCC
VSS
Type
O
I
I
I
I
I
I
I
I
Name and Function
BUS HOLD ACKNOWLEDGE output indicates that the 80376 has
surrendered control of its local bus to another bus master See Bus
Arbitration Signals in Section 4 1 for additional information
INTERRUPT REQUEST is a maskable input that signals the 80376 to
suspend execution of the current program and execute an interrupt
acknowledge function See Interrupt Signals in Section 4 1 for
additional information
NON-MASKABLE INTERRUPT REQUEST is a non-maskable input
that signals the 80376 to suspend execution of the current program
and execute an interrupt acknowledge function See Interrupt Signals
in Section 4 1 for additional information
BUSY signals a busy condition from a processor extension See
Coprocessor Interface Signals in Section 4 1 for additional
information
ERROR signals an error condition from a processor extension See
Coprocessor Interface Signals in Section 4 1 for additional
information
PROCESSOR EXTENSION REQUEST indicates that the processor
extension has data to be transferred by the 80376 See Coprocessor
Interface Signals in Section 4 1 for additional information
FLOAT when active forces all bidirectional and output signals
including HLDA to the float condition FLOAT is not available on the
PGA package See Float for additional information
NO CONNECT should always remain unconnected Connection of a
N C pin may cause the processor to malfunction or be incompatible
with future steppings of the 80376
SYSTEM POWER provides the a5V nominal D C supply input
SYSTEM GROUND provides 0V connection from which all inputs and
outputs are measured
2 0 ARCHITECTURE OVERVIEW
The 80376 supports the protection mechanisms
needed by sophisticated multitasking embedded
systems and real-time operating systems The use
of these protection mechanisms is completely op-
tional For embedded applications not needing pro-
tection the 80376 can easily be configured to pro-
vide a 16 Mbyte physical address space
Instruction pipelining high bus bandwidth and a
very high performance ALU ensure short average
instruction execution times and high system
throughput The 80376 is capable of execution at
sustained rates of 2 5–3 0 million instructions per
second
The 80376 offers on-chip testability and debugging
features Four break point registers allow conditional
or unconditional break point traps on code execution
or data accesses for powerful debugging of even
ROM based systems Other testability features in-
clude self-test and tri-stating of output buffers during
RESET
The Intel 80376 embedded processor consists of a
central processing unit a memory management unit
and a bus interface The central processing unit con-
sists of the execution unit and instruction unit The
execution unit contains the eight 32-bit general reg-
isters which are used for both address calculation
and data operations and a 64-bit barrel shifter used
to speed shift rotate multiply and divide operations
The instruction unit decodes the instruction opcodes
and stores them in the decoded instruction queue
for immediate use by the execution unit
The Memory Management Unit (MMU) consists of a
segmentation and protection unit Segmentation al-
lows the managing of the logical address space by
providing an extra addressing component one that
allows easy code and data relocatability and effi-
cient sharing
The protection unit provides four levels of protection
for isolating and protecting applications and the op-
erating system from each other The hardware en-
forced protection allows the design of systems with
a high degree of integrity and simplifies debugging
Finally to facilitate high performance system hard-
ware designs the 80376 bus interface offers ad-
dress pipelining and direct Byte Enable signals for
each byte of the data bus
6

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376 pdf, datenblatt
376 EMBEDDED PROCESSOR
Table 2 3 Segment Register Selection Rules
Type of
Memory Reference
Implied (Default)
Segment Use
Code Fetch
CS
Destination of PUSH PUSHF INT
CALL PUSHA Instructions
SS
Source of POP POPA POPF IRET
RET Instructions
SS
Destination of STOS
MOVS REP STOS
REP MOVS Instructions
(DI is Base Register)
ES
Other Data References
with Effective Address
Using Base Register of
EAX
EBX
ECX
EDX
ESI
EDI
EBP
ESP
DS
DS
DS
DS
DS
DS
SS
SS
Segment Override
Prefixes Possible
None
None
None
None
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
CS SS ES FS GS
2 4 Addressing Modes
The 80376 provides a total of 8 addressing modes
for instructions to specify operands The addressing
modes are optimized to allow the efficient execution
of high level languages such as C and FORTRAN
and they cover the vast majority of data references
needed by high-level languages
Two of the addressing modes provide for instruc-
tions that operate on register or immediate oper-
ands
Register Operand Mode The operand is located in
one of the 8- 16- or 32-bit general registers
Immediate Operand Mode The operand is includ-
ed in the instruction as part of the opcode
The remaining 6 modes provide a mechanism for
specifying the effective address of an operand The
linear address consists of two components the seg-
ment base address and an effective address The
effective address is calculated by summing any
combination of the following three address elements
(see Figure 2 3)
DISPLACEMENT an 8- 16- or 32-bit immediate val-
ue following the instruction
BASE The contents of any general purpose regis-
ter The base registers are generally used by compil-
ers to point to the start of the local variable area
Note that if the Address Length Prefix is used only
BX and BP can be used as a BASE register
INDEX The contents of any general purpose regis-
ter except for ESP The index registers are used to
access the elements of an array or a string of char-
acters The index register’s value can be multiplied
by a scale factor either 1 2 4 or 8 The scaled index
is especially useful for accessing arrays or struc-
tures Note that if the Address Length Prefix is
used no Scaling is available and only the registers
SI and DI can be used to INDEX
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