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33984 Schematic ( PDF Datasheet ) - Motorola Inc

Teilenummer 33984
Beschreibung Dual Intelligent High-Current Self-Protected Silicon High-Side Switch (4.0 m)
Hersteller Motorola Inc
Logo Motorola  Inc Logo 




Gesamt 28 Seiten
33984 Datasheet, Funktion
MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33984
Rev 4.0, 09/2004
Advance Information
Dual Intelligent High-Current
Self-Protected Silicon High-Side
Switch (4.0 mΩ)
The 33984 is a dual self-protected 4.0 msilicon switch used to replace
electromechanical relays, fuses, and discrete devices in power management
applications. The 33984 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and pulse-width modulation (PWM) control of each output. SPI-programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.
The 33984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN
package with exposed tabs.
Features
• Dual 4.0 mMax High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring with Two SPI-Selectable Current Ratios
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Pin Status, and Program Status
• Enhanced -16 V Reverse Polarity VPWR Protection
33984
DUAL HIGH-SIDE SWITCH
4.0 m
Bottom View
SCCPANSAAELS1UE4F02F1-I0X:21
16-TERMINAL PQFN (12 x 12)
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33984PNA/R2 -40°C to 125°C 16 PQFN
33S9im8p4lifSieidmAppplilficieatdionADpipaglircamation Diagram
VDD VDD
I/O
I/O
SO
SCLK
MCU
CS
SI
I/O
I/O
I/O
A/D
VDD VPWR
33984
VDD VPWR
FS GND
WAKE
SI HS1
SCLK
CS
SO
RST HS0
IN0
IN1
CSNS
FSI GND
LOAD
LOAD
GND PWR GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com






33984 Datasheet, Funktion
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40°C TJ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
POWER INPUT
Battery Supply Voltage Range
Full Operational
VPWR
V
6.0 – 27
VPWR Operating Supply Current
Output ON, IHS0 and IHS1 = 0 A
IPWR(ON)
mA
– 20
VPWR Supply Current
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
RST = VLOGIC HIGH
IPWR(SBY)
mA
– 5.0
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
TJ = 25°C
TJ = 85°C
IPWR(SLEEP)
µA
– 10
– 50
VDD Supply Voltage
VDD(ON) 4.5 5.0 5.5 V
VDD Supply Current
No SPI Communication
3.0 MHz SPI Communication
VDD Sleep State Current
IDD(ON)
IDD(SLEEP)
mA
1.0
5.0
– 5.0 µA
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown Threshold (Note 8)
Undervoltage Hysteresis (Note 9)
Undervoltage Power-ON Reset
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
VPWR(UVHYS)
VPWR(UVPOR)
28
0.2
5.0
32 36 V
0.8 1.5 V
5.5 6.0 V
0.25 – V
– 5.0 V
Notes
8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
9. This applies when the undervoltage fault is not latched (IN[0:1] = 0).
33984
6
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com

6 Page









33984 pdf, datenblatt
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40°C TJ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
Required Low State Duration for RST (Note 24)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25)
f SPI
t WRST
t CS
– 3.0 MHz
50 350 ns
– 300 ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
Required High State Duration of SCLK (Required Setup Time) (Note 25)
Required Low State Duration of SCLK (Required Setup Time) (Note 25)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25)
SI to Falling Edge of SCLK (Required Setup Time) (Note 26)
Falling Edge of SCLK to SI (Required Setup Time) (Note 26)
SO Rise Time
CL = 200 pF
t ENBL
t LEAD
t WSCLKh
t WSCLKl
t LAG
t SI(SU)
t SI(HOLD)
t RSO
– 5.0 µs
50 167 ns
– 167 ns
– 167 ns
50 167 ns
25 83 ns
25 83 ns
ns
25 50
SO Fall Time
CL = 200 pF
t FSO
ns
25 50
SI, CS, SCLK, Incoming Signal Rise Time (Note 26)
SI, CS, SCLK, Incoming Signal Fall Time (Note 26)
Time from Falling Edge of CS to SO Low Impedance (Note 27)
Time from Rising Edge of CS to SO High Impedance (Note 28)
Time from Rising Edge of SCLK to SO Data Valid (Note 29)
0.2 VDD SO 0.8 VDD, CL = 200 pF
t RSI
t RSI
t SO(EN)
t SO(DIS)
t VALID
– 50 ns
– 50 ns
– 145 ns
65 145 ns
ns
65 105
Notes
24. RST low duration measured with outputs enabled and going to OFF or disabled condition.
25. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27. Time required for output status data to be available for use at SO. 1.0 kon pullup on CS.
28. Time required for output status data to be terminated at SO. 1.0 kon pullup on CS.
29. Time required to obtain valid data out from SO following the rise of SCLK.
33984
12
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com

12 Page





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