PDF 3256E Data sheet ( Hoja de datos )

Número de pieza	3256E
Descripción	In-System Programmable High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 3256E In-System Programmable High Density PLD Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 256 I/O Pins — 12000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100 MHz Maximum Operating Frequency — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable (ISP™) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Five Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Mini- mize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram ORP ORP H3 H2 H1 H0 ORP ORP G3 G2 G1 G0 Boundary Scan A0 D Q F3 A1 DQ OR F2 A2 Array D Q F1 DQ A3 Twin F0 D Q GLB DQ OR B0 Array D Q E3 B1 D Q E2 B2 E1 Global Routing Pool B3 E0 C0 C1 C2 C3 ORP ORP D0 D1 D2 D3 ORP ORP Description 0139A/3256E The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these ele- ments. The ispLSI 3256E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3256E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 3256E device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. There are a total of 32 Twin GLBs in the ispLSI 3256E device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays and eight outputs which can be configured to be either combinato- rial or registered. All Twin GLB inputs come from the GRP. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com June 2002 3256e_08 1 1 page Specifications ispLSI 3256E Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V ≤ 3ns 10% to 90% 1.5V 1.5V See Figure 2 Table 2-0003/3256E Figure 2. Test Load Device Output + 5V R1 R2 Test Point CL* Output Load conditions (See Figure 2) TEST CONDITION A Active High B Active Low Active High to Z C at VOH -0.5V Active Low to Z at VOL+0.5V R1 470Ω ∞ 470Ω ∞ R2 390Ω 390Ω 390Ω 390Ω CL 35pF 35pF 35pF 5pF 470Ω 390Ω 5pF Table 2 - 0004A *CL includes Test Fixture and Probe Capacitance. 0213A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION MIN. TYP.3 MAX. UNITS VOL Output Low Voltage IOL= 8 mA – – 0.4 V VOH Output High Voltage IOH = -4 mA 2.4 – – V IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA IIL-isp Bscan/ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA IIL-PU I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA IOS1 Output Short Circuit Current VCC= 5V, VOUT = 0.5V – – -200 mA ICC2,4 Operating Power Supply Current VIL= 0.0V, VIH= 3.0V fTOGGLE = 1 MHz – 300 – mA Table 2 - 0007isp/3256E 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using sixteen 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25°C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 5 5 Page Specifications ispLSI 3256E Pin Description Pin Name I/O Description Input/Output pins – These are the general purpose I/O pins used by the logic array. GOE0, GOE1 Global Output Enable input pins. TOE RESET Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven. Active Low (0) Reset pin – Resets all of the GLB and I/O registers in the device. Y0, Y1, Y2 Y3, Y4 BSCAN/ispEN TDI/SDI TCK/SCLK TMS/MODE TRST/NC1 TDO/SDO Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells on the device. Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in the high-Z state. Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the ISP State Machine. Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine. Input – Test Reset, active low to reset the Boundary Scan State Machine. Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the ISP data. When ispEN is high, it functions as Test Data Out. GND Ground (GND) VCC NC1 Vcc No Connect. 1. NC pins are not to be connected to any active signals, VCC or GND. Pin Locations Signal GOE0, GOE1 TOE RESET Y0, Y1, Y2, Y3, Y4 ispEN/BSCAN SDI/TDI SCLK/TCK MODE/TMS TRST/NC1 SDO/TDO GND VCC NC1 304-Pin PQFP 195, 185 215 53 43, 33, 205, 175, 165 63 23 73 13 225 155 9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171, 191, 201, 221, 237, 247, 267, 277, 297 1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257, 287, 304 320-Ball BGA AD11, AC14 AC6 A17 A14, B11, AD8, AB16, AA18 B19 C9 D20 D7 AA5 AB21 D6, C8, B13, A16, D19, F21, H22, N23, T24, W21, AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4 D4, B10, B18, D21, K23, V23, AA21, AC15, AC7, AA4, R2, G2, C3 A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2, AC23, AC24, AD1, AD2, AD23, AD24 1. NC pins are not to be connected to any active signals, VCC or GND. 11 11 Page

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