|
|
PDF CXL5504P Data sheet ( Hoja de datos )
| Número de pieza | CXL5504P | |
| Descripción | CMOS-CCD 1H Delay Line for NTSC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CXL5504P (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
CXL5504M/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
Features
• Single power supply (5V)
• Low power consumption 90mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
• Operating temperature Topr –10 to +60
• Storage temperature Tstg –55 to +150
• Allowable power dissipation
PD
CXL5504M 350
CXL5504P 480
V
°C
°C
mW
mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.4 to 1.0 Vp-p
(0.5Vp-p typ.)
• Clock frequency
fCLK 14.318182 MHz
• Input clock waveform Sine wave
Blook Diagram and Pin Configration (Top View)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
876 5
Autobias circuit
Bias circuit
CCD
(905bit)
Clamp circuit
1
Output circuit
(S/H 1bit)
I/O control
23
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89931C79-PS
1 page  
CXL5504M/P
(7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
Clock
fsc (14.318182MHz) sine wave
0.4 to 1.0Vp-p
(0.5Vp-p typ.)
–5–
5 Page 
CXL5504P
8PIN DIP (PLASTIC)
+ 0.4
9.4 – 0.1
85
1
2.54
4
0° to 15°
0.5 ± 0.1
1.2 ± 0.15
SONY CODE
EIAJ CODE
JEDEC CODE
DIP-8P-01
DIP008-P-0300
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
LEAD MATERIAL
PACKAGE MASS
COPPER ALLOY
0.5g
CXL5504M/P
– 11 –
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CXL5504P.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CXL5504M | CMOS-CCD 1H Delay Line for NTSC | Sony Corporation |
| CXL5504P | CMOS-CCD 1H Delay Line for NTSC | Sony Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |