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Número de pieza | CXL1518M | |
Descripción | CMOS-CCD Signal Processor | |
Fabricantes | Sony Corporation | |
Logotipo | ||
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No Preview Available ! CXL1517M/1518M
CMOS-CCD Signal Processor
Description
The CXL1517M/1518M are CMOS-CCD signal
processors developed for CCD camera complementary
color filter array processing system.
CXL1517M
452.5-bit × 2, 453.5-bit 1H CCD delay line
CXL1518M
300.5-bit × 2, 301.5-bit 1H CCD delay line
20 pin SOP (Plastic)
Features
• Single 5V power supply
• Low power consumption (Typ.)
CXL1517M 120mW
CXL1518M 75mW
• Built-in peripheral circuits
• Built-in CDS (Correlated Double Sampling) circuit
Structure
CMOS-CCD
Functions
• Clock driver
• Autobias circuit (Center and black)
• Pedestal clamp circuit
• CDS circuit
• Overflow prevention circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
• Operating temperature
Topr
• Storage temperature
Tstg
• Allowable power dissipation
PD
6
–10 to +65
–55 to +150
500
V
°C
°C
mW
Recommended Operating Voltage Range (Ta = 25°C)
Supply voltage
VDD 4.6 to 5.25
V
Item
Clock voltage Low
Clock voltage High
Clock
frequency
CXL1517M
CXL1518M
Symbol
VL
VH
Min.
VSS
0.7 × VDD
fCL
fCL
Typ.
7.16
4.77
Max.
0.3 × VDD
VDD
Unit
V
V
MHz
MHz
Remarks
NTSC: 455fH
CCIR: 454fH
NTSC: 910fH/3
CCIR: 908fH/3
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E91777A78-PS
1 page CXL1517M/1518M
Notes)
1) Linearity testing
For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a
sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C
channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then
input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum
output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output
amplitude as Sout min. The linearity of the respective channels is defined as:
Lin. = Sout max – Sout min × 200 [%]
Sout max + Sout min
2) Calculation of insertion gain difference
As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin,
the insertion gain difference between channels ∆G as:
( )∆G = | 1 – 10
Gmax – Gmin
20
| × 100 [%]
3) Calculation of linearity difference
Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as:
∆LBC = | LB – LC | [%]
4) Cross-talk calculation
CRTa
: The cross-talk value of A channel when B and C channels are input
OUTA-a : The output value of A channel when A channel is input
SW3-a, SW4-a, SW5, 6-b
OUTA-bc : The output value of A channel when B and C channels are input
(Cross-talk component)
SW3-a, SW4-b, SW5, 6-a
CRTa =
OUTA-bc
OUTA-a
× 100 [%]
Clock Waveform Timing
(52.5) ∗
87.5ns
10ns
10ns
(140) ∗
210ns
XDL1
90%
50%
10%
90%
50%
10%
17.5ns
(52.5) ∗
87.5ns
10ns
10ns
XDL2
90%
50%
10%
–5–
90%
50%
10%
∗ The value in brackets is for CXL1517M.
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet CXL1518M.PDF ] |
Número de pieza | Descripción | Fabricantes |
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