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Número de pieza | CXK5V8512TM-85LLX | |
Descripción | 65536-word X 8-bit High Speed CMOS Static RAM | |
Fabricantes | Sony Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CXK5V8512TM-85LLX (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
No Preview Available ! CXK5V8512TM -85LLX/10LLX
65536-word × 8-bit High Speed CMOS Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK5V8512TM is a high speed CMOS static
RAM organized as 65536-words by 8-bits.
A polysilicon TFT cell technology realized
extremely low stand-by current and higher data
retention stability.
Operating on a single 3.3V supply, and special
feature are low power consumption, high speed.
The CXK5V8512TM is a suitable RAM for portable
equipment with battery back up.
32 pin TSOP (Plastic)
Features
• Extended operating temperature range:
–25 to +85°C
• Fast access time:
(Access time)
-85LLX
85ns (Max.)
-10LLX
100ns (Max.)
• Low standby current:
14µA (Max.)
• Low data retention current: 12µA (Max.)
• Single 3.3V supply:
3.3V ± 0.3V
• Low voltage data retention: 2.0V (Min.)
• Package
8mm × 20mm 32 pin TSOP package
Function
65536-word × 8-bit static RAM
Structure
Silicon gate CMOS IC
Block Diagram
A15
A13
A8
A11
A9
A7 Buffer
A6
A5
A14
A12
A4
A3
A10
A0
A2
A1
OE
WE
CE1
CE2
Buffer
Buffer
Row
Decoder
Memory
Matrix
1024 × 512
I/O Gate
Column
Decoder
I/O Buffer
I/O1 I/O8
VCC
GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95716-PP
1 page CXK5V8512TM
• Read cycle (WE = “H”)
(Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C)
Item
Read cycle time
Symbol
tRC
-85LLX
Min. Max.
85 —
-10LLX
Min. Max.
100 —
Unit
ns
Address access time
tAA — 85 — 100 ns
Chip enable access time (CE1)
tCO1 — 85 — 100 ns
Chip enable access time (CE2)
tCO2 — 85 — 100 ns
Output enable to output valid
tOE — 40 — 50 ns
Output hold from address change tOH 10 — 10 — ns
Chip enable to output in low Z (CE1, CE2) tLZ1, tLZ2
10 — 10 — ns
Output enable to output in low Z (OE)
tOLZ
5 — 5 — ns
Chip disable to output in high Z (CE1, CE2) tHZ1∗, tHZ2∗ — 35 — 40 ns
Output disable to output in high Z (OE)
tOHZ∗
— 30 — 35 ns
∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
(Vcc = 3.3V ± 0.3V, GND = 0V, Ta = –25 to +85°C)
-85LLX
-10LLX
Item Symbol
Unit
Min. Max. Min. Max.
Write cycle time
tWC 85 — 100 — ns
Address valid to end of write
tAW 70 — 80 — ns
Chip enable to end of write
tCW 70 — 80 — ns
Data to write time overlap
tDW 35 — 40 — ns
Data hold from write time
tDH 0 — 0 — ns
Write pulse width
tWP 60 — 70 — ns
Address setup time
tAS 0 — 0 — ns
Write recovery time (WE)
tWR 5 — 5 — ns
Write recovery time (CE1, CE2)
tWR1
5 — 5 — ns
Output active from end of write
Write to output in high Z
tOW
tWHZ∗
5 — 5 — ns
— 35 — 40 ns
∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet CXK5V8512TM-85LLX.PDF ] |
Número de pieza | Descripción | Fabricantes |
CXK5V8512TM-85LLX | 65536-word X 8-bit High Speed CMOS Static RAM | Sony Corporation |
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