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PDF CXK5T16100TM-12LLX Data sheet ( Hoja de datos )
| Número de pieza | CXK5T16100TM-12LLX | |
| Descripción | 65536-word x 16-bit High Speed CMOS Static RAM | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXK5T16100TM -12LLX
65536-word × 16-bit High Speed CMOS Static RAM Preliminary
For the availability of this product, please contact the sales office.
Description
The CXK5T16100TM is a general purpose high
44 pin TSOP (PIastic)
speed CMOS static RAM organized as 65536-
words by 16-bits.
Special feature are low power consumption and
high speed.
The CXK5T16100TM is a suitable RAM for portable
equipment with battery back up.
Features
• Extended operating temperature range: –25 to +85°C
• Wide supply voltage range operation: 2.7 to 3.6V
• Fast access time:
(Access time)
3.0V operation 120ns (max.)
3.3V operation 100ns (max.)
• Low power consumption operation:
Standby / DC operation
1.6µW (typ.) / 3.3mW (typ.)
100µW (max.) / 11mW (max.)
• Fully static memory ··· No clock or timing strobe
required
• Equal access and cycle time
• Common data input and output: three state output
• Directly LVTTL compatible: All inputs and outputs
• Low voltage data retention: 2.0V (min.)
• 400mil 44pin TSOP (type II) package
Function
65536-word x 16-bit static RAM
Block Diagram
A1
A0
A7
A6
A5 Buffer
A4
Vcc Vcc
A3
Memory
Row
Memory
A2
Matrix
512 × 1024
Decoder
Matrix
512 × 1024
A15 GND
GND
A14
CE
UB
LB Control
OE
WE
I/O Gate
Column
Decoder
Pre
Decoder
I/O Gate
Column
Decoder
A13
A12
A11
Buffer
A10
A9
A8
I/O Buffer
I/O Buffer
I/O1 I/O8
I/O9 I/O16
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE96405-ST
1 page  
CXK5T16100TM
• Read cycle (WE = “H”)
Item
VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V
Symbol
Unit
Min. Max. Min. Max.
Read cycle time
tRC 120 — 100 — ns
Address access time
Chip enable access time (CE)
tAA — 120 — 100 ns
tCO — 120 — 100 ns
Byte enable access time (UB, LB)
Output enable to output valid
tBO — 60 — 50 ns
tOE — 60 — 50 ns
Output hold from address change
tOH 10 — 10 — ns
Chip enable to output in low Z (CE) tLZ 10 — 10 — ns
Output enable to output in low Z (OE)
tOLZ
5
—
5
— ns
Byte enable to output in low Z (UB, LB) tBLZ 5 — 5 — ns
Chip disable to output in high Z (CE)
tHZ∗1
—
40
—
40 ns
Chip disable to output in high Z (OE)
tOHZ∗1
—
35
—
35 ns
Byte disable to output in high Z (UB, LB) tBHZ∗1
—
35
—
35 ns
∗1 tHZ, tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Item
VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V
Symbol
Unit
Min. Max. Min. Max.
Write cycle time
tWC 120 — 100 — ns
Address valid to end of write
tAW 100 — 80 — ns
Chip enable to end of write
tCW 100 — 80 — ns
Byte enable to end of write
tBW 100 — 80 — ns
Data to write time overlap
tDW 50 — 40 — ns
Data hold from write time
tDH 0 — 0 — ns
Write pulse width
tWP 70 — 70 — ns
Address setup time
tAS 0 — 0 — ns
Write recovery time (WE)
tWR 5 — 5 — ns
Write recovery time (CE, UB, LB)
tWR1
5
—
5
— ns
Output active from end of write
Write to output in high Z
tOW 5 — 5 — ns
tWHZ∗2
—
40
—
40 ns
∗2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage levels.
–5–
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CXK5T16100TM-12LLX.PDF ] | |
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