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PDF CXD3068Q Data sheet ( Hoja de datos )
| Número de pieza | CXD3068Q | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD3068Q
CD Digital Signal Processor with Built-in Digital Servo Preliminary
Description
The CXD3068Q is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo.
Features
• All digital signal processings during playback are
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 4× continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 4× playback variable pitch
playback
• Bit clock, which strobes the EFM signal, is
generated by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 4× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface output
• Digital level meter, peak meter
• Bilingual supported
• VCO control mode
• CD TEXT data demodulation
• EFM playability reinforcement function
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
80 pin QFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.5 to +4.6 V
• Input voltage VI –0.5 to +4.6 V
(VSS – 0.5V to VDD + 0.5V)
• Output voltage
VO
–0.5 to +4.6 V
(VSS – 0.5V to VDD + 0.5V)
• Storage temperature Tstg
–55 to +150 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Note) AVDD includes XVDD and AVSS includes XVSS.
Recommended Operating Conditions
• Supply voltage
VDD
2.7 to 3.6
• Operating temperature
Topr
–20 to +75
V
°C
Input/Output Capacitance
• Input pin
CI
• Output pin
CO
• I/O pin
CI/O
Note) Measurement conditions
9 (Max.)
11 (Max.)
11 (Max.)
VDD = VI = 0V
fM = 1MHz
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE00326-PS
1 page  
CXD3068Q
Pin
No.
Symbol
I/O
Description
34 FRDR O 1, 0 Focus drive output.
35 DVSS1 — —
Digital GND.
36 TEST
I
Test. Normally, GND.
37 TES1
I
Test. Normally, GND.
38 VC
I
Center voltage input.
39 FE
I
Focus error signal input.
40 SE
I
Sled error signal input.
41 TE
I
Tracking error signal input.
42 CE
I
Center servo analog input.
43 RFDC I
RF signal input.
44 ADIO
O Analog Test. No connected.
45 AVSS0 — —
Analog GND.
46 IGEN
I
Constant current input for operational amplifier.
47 AVDD0 — —
Analog power supply.
48 ASYO O 1, 0 EFM full-swing output. (low = Vss, high = VDD)
49 ASYI
I
Asymmetry comparator voltage input.
50 RFAC I
EFM signal input.
51 AVSS1 — —
Analog GND.
52 CLTV
I
Multiplier VCO1 control voltage input.
53 FILO
O Analog Master PLL filter output (slave = digital PLL).
54 FILI
I
Master PLL filter input.
55 PCO
O 1, Z, 0 Master PLL charge pump output.
56 AVDD1 — —
Analog power supply.
57 BIAS
I
Asymmetry circuit constant current input.
58 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
59 V16M
I/O 1, 0
Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM
PLL clock input by switching with the command.
60 VPCO O 1, Z, 0 Wide-band EFM PLL charge pump output.
61 DVDD2 — —
Digital power supply.
62 ASYE
I
Asymmetry circuit on/off (low = off, high = on).
63 MD2
I
Digital Out on/off control (low = off, high = on).
64 DOUT O 1, 0 Digital Out output.
65 LRCK O 1, 0 D/A interface. LR clock output. f = Fs
66 PCMD O 1, 0 D/A interface. Serial data output (two's complement, MSB first).
67 BCK
O 1, 0 D/A interface. Bit clock output.
–5–
5 Page 
CXD3068Q
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing .................................................................................................................... 12
§ 1-2. CPU Interface Command Table .................................................................................................... 12
§ 1-3. CPU Command Presets ................................................................................................................ 23
§ 1-4. Description of SENS Signals ......................................................................................................... 30
[2] Subcode Interface
§ 2-1. P to W Subcode Readout .............................................................................................................. 57
§ 2-2. 80-bit Sub-Q Readout.................................................................................................................... 57
[3] Description of Modes
§ 3-1. CLV-N Mode.................................................................................................................................. 64
§ 3-2. CLV-W Mode ................................................................................................................................. 64
§ 3-3. CAV-W Mode................................................................................................................................. 64
§ 3-4. VCO-C mode ................................................................................................................................. 65
[4] Description of Other Functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit ...................................................................... 68
§ 4-2. Frame Sync Protection .................................................................................................................. 70
§ 4-3. Error Correction ............................................................................................................................. 70
§ 4-4. DA Interface................................................................................................................................... 71
§ 4-5. Digital Out...................................................................................................................................... 73
§ 4-6. Servo Auto Sequence.................................................................................................................... 74
§ 4-7. Digital CLV..................................................................................................................................... 82
§ 4-8. Playback Speed............................................................................................................................. 83
§ 4-9. Asymmetry Correction ................................................................................................................... 84
§ 4-10. CD TEXT Data Demodulation ....................................................................................................... 85
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System.............................................................. 87
§ 5-2. Digital Servo Block Master Clock (MCK) ....................................................................................... 88
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ....................................................... 89
§ 5-4. E: F Balance Adjustment Function ................................................................................................ 90
§ 5-5. FCS Bias Adjustment Function...................................................................................................... 90
§ 5-6. AGCNTL Function ......................................................................................................................... 92
§ 5-7. FCS Servo and FCS Search ......................................................................................................... 94
§ 5-8. TRK and SLD Servo Control ......................................................................................................... 95
§ 5-9. MIRR and DFCT Signal Generation .............................................................................................. 96
§ 5-10. DFCT Countermeasure Circuit ...................................................................................................... 97
§ 5-11. Anti-Shock Circuit .......................................................................................................................... 97
§ 5-12. Brake Circuit .................................................................................................................................. 98
§ 5-13. COUT Signal ................................................................................................................................. 99
§ 5-14. Serial Readout Circuit.................................................................................................................... 99
§ 5-15. Writing to Coefficient RAM ............................................................................................................ 100
§ 5-16. PWM Output .................................................................................................................................. 100
§ 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 101
§ 5-18. Description of Commands and Data Sets ..................................................................................... 101
§ 5-19. List of Servo Filter Coefficients...................................................................................................... 124
§ 5-20. Filter Composition.......................................................................................................................... 126
§ 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 132
[6] Application Circuit .................................................................................................................................. 133
Explanation of abbreviations
AVRG:
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
Average
Auto gain control
Focus
Tracking
Sled
Defect
– 11 –
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet CXD3068Q.PDF ] | |
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