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PDF CXD1914Q Data sheet ( Hoja de datos )
| Número de pieza | CXD1914Q | |
| Descripción | Digital Video Encoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD1914Q
Digital Video Encoder
For the availability of this product, please contact the sales office.
Description
The CXD1914Q is a digital video encoder
designed for DVDs, set top boxes, digital VCRs and
other digital video equipment. This device accepts
ITU-R601 compatible Y, Cb and Cr data, and the
data are encoded to composite video and separate
Y/C video (S-video) signals and converted to
RGB/YUV signals.
100 pin QFP (Plastic)
Features
• NTSC and PAL encoding modes
• Composite video and separate Y/C video (S-video)
signal output
• R, G, B/Y, U and V (BetaCam/SMPTE level) signal
output
• 8/16-bit pixel data input modes
• 13.5 Mpps pixel rate
• 10-bit 6-channel DAC
• Supports I2C bus (400 kHz) and Sony SIO
• Closed Caption (Line 21, Line 284) encoding
• Macrovision Pay-Per-View copy protection system
: NTSC Rev. 7.0, PAL Rev. 6.1 (Note 1)
• VBID encoding
• WSS encoding
• Supports non-interlace mode
• Monolithic CMOS single 5.0 V power supply
• 100-pin plastic QFP
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD –0.3 to +7.0
• Input voltage
VI –0.3 to +7.0
• Output voltage
VO –0.3 to +7.0
• Operating temperature Topr –20 to +75
• Storage temperature Tstg –40 to +125
(VSS=0 V)
V
V
V
°C
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.75 to 5.25
• Input voltage
VIN VSS to VDD
• Operating temperature Topr 0 to +70
V
V
°C
I/O Pin Capacitance
• Input pin
• Output pin
CI 11 (Max.) pF
CO 11 (Max.) pF
Note) Test conditions : VDD=VI=0 V, fM=1 MHz
(Note 1)
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights.
Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E96Z29-TE
1 page  
CXD1914Q
Pin
Symbol
No.
47 SI/SDA
48 SO
49 NC
50 NC
51 NC
52 NC
53 NC
54 IREF
55 VREF
56 CP-OUT
57 AVDD1
58 C-OUT
59 AVSS1
60 NC
61 VB
62 VG
63 NC
64 Y-OUT
65 AVDD2
66 B-OUT
67 AVSS2
68 NC
69 NC
70 NC
71 NC
72 G-OUT
73 AVDD3
74 R-OUT
75 AVSS3
76 NC
77 NC
78 NC
79 NC
80 NC
81 VDD4
I/O Description
This pin’s function is selected by XIICEN (Pin 43).
I/O When XIICEN = “H”, this pin is Sony SIO mode ; SI serial data input.
When XIICEN = “L”, this pin is I2C bus mode ; SDA input/output.
This pin’s function is selected by XIICEN (Pin 43).
O When XIICEN = “H”, this pin is Sony SIO mode ; SO serial out output.
When XIICEN = “L”, this pin is not used and output is high impedance.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
DAC reference current input.
I
Connect resistance “16R” which is 16 times output resistance “R”.
DAC reference voltage input.
I
Sets the DAC output full-scale width.
O 10-bit DAC output. This pin outputs the composite signal.
— Analog power supply.
O 10-bit DAC output. This pin outputs the chroma (C) signal.
— Analog ground.
— Not connected inside the IC.
O Connect to ground via a capacitor of approximately 0.1 µF.
O Connect to analog power supply via a capacitor of approximately 0.1 µF.
— Not connected inside the IC.
O 10-bit DAC output. This pin outputs the luminance (Y) signal.
— Analog power supply.
O 10-bit DAC output. This pin outputs the B and V signals.
— Analog ground.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
O 10-bit DAC output. This pin outputs the G and Y signals.
— Analog power supply.
O 10-bit DAC output. This pin outputs the R and U signals.
— Analog ground.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Not connected inside the IC.
— Digital power supply.
—5—
5 Page 
CXD1914Q
Description of Functions
The CXD1914Q converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC
(RS170A) or PAL (ITU-R624; B, G, H, I) format.
The CXD1914Q first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr
signals into the U and V signals, respectively, interpolates 4 : 2 : 2 to 4 : 4 : 4, and then modulates the
signals with the digital subcarrier inside the CXD1914Q to create the chroma (C) signal.
The Y and chroma (C) signals are oversampled at double speed to reduce sin (X) / X roll-off, and then
added to become the digital composite signal.
The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.
1. Pixel input format
The pixel input format is selected according to the value (bit 4 of address 01H) of control register “PIF
MODE” as shown in Table 1-1 below.
When “PIF MODE” is “0”, the image data (multiplexed Y, Cb, and Cr data) input from PD0 to 7 are sampled
at the rising edge of SYSCLK as shown in the chart on the following page. When “PIF MODE” is “1”, the
image data (PD0 to 7 : Y data, PD8 to 15 : multiplexed Cb and Cr data) input from PD0 to 15 are sampled
at the rising edge of PDCLK.
PIF MODE
0 (8-bit mode)
1 (16-bit mode)
PD15 to 8
N/A
Cb/Cr
Table 1-1
PD7 to 0
Y/Cb/Cr
Y
Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register
address 01H as shown in Table 1-2 below.
When “PIF MODE” is “0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to 7 is sampled at
the rising edge of SYSCLK after the fall of HSYNC.
(Default : Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)
When “PIF MODE” is “1”, Y0 and Y1 data are input to PD0 to 7, multiplexed Cb0 and Cr0 data are input to
PD8 to 15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC.
(Default : Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)
PIX TIM
00
01
10
11
Timing phase
#0 (default)
#1
#2
#3
Table 1-2
—11—
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1914Q.PDF ] | |
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