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PDF CXD1217 Data sheet ( Hoja de datos )
| Número de pieza | CXD1217 | |
| Descripción | Synchronizing Signal Generator for Video Camera | |
| Fabricantes | Sony Corporation | |
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CXD1217M
Synchronizing Signal Generator for Video Camera
Description
The CXD1217M is a synchronizing signal generator
for color video cameras.
Features
• Compatible with the respective systems, NTSC,
PALM, PAL and SECAM
• Output is synchronized with the clock of 910fH or
908fH
• 25Hz offset processing by PAL system
• Color framing by the respective systems, NTSC,
PALM and PAL
• Possible external synchronization by H reset, V
reset and line alternate reset pins
Applications
Synchronizing signal generator for color video
cameras
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD VSS – 0.5 to +7.0 V
• Input voltage
VI VSS – 0.5 to VDD + 0.5 V
• Output voltage
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature Topr
–20 to +75
°C
• Storage temperature Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.5 to 5.5
• Operating temperature Topr
–20 to +75
V
°C
28 pin SOP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89626A79-PS
1 page  
CXD1217M
Description of Operation (See Block Diagram.)
The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them,
the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted .
NTSC
PAL
PALM
SECAM
Sub carrier
4fsc = 910fH
4fsc = 1135fH + 2fv
4fsc = 909fH
—
Clock
910fH
908fH
910fH
908fH
As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the
PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL.
1 . MODE specified input
The CXD1217 provides four inputs to specify the respective modes.
∗ EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the
counters in connection with the PLL Ioop as shown in the upper part of the block diagram
become into stand still state.
∗ MODE1 and MODE2 inputs: These are inputs for the system selection.
MODE1
MODE2
System
0 0 NTSC
0 1 SECAM
1
0
PALM
"0" → VSS
11
PAL
"1" → VDD
∗ TEST input: An input to be used to measure IC. This input is normally kept opened.
(Because it is dropped internally to Vss with MOS resistance.)
2. Reset operation
The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation
when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC
internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched
as a reset operation to each other (GEN Iocked).
• H reset (HRI input)
When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge,
and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns)
against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed.
The minimum resetting pulse width is over 0.3µs.
The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as
shown in the diagram below.
HRI input
CXD1217
HD OUT output
Reset
–5–
6.3 to 6.37 [µs]
5 Page 
CXD1217M
• PALM
OSC
14.318MHz ( = 910fH)
L. P. F VCO
VDD
10k
4fsc
IN
10
19
1/4
9
4fsc
OUT
14.302MHz
(4fsc)
S. C.
Reset
1/9
1/8
24
HCOMOUT
26 25 14
CLIN CLOUT VSS
28 21
VDD MODE1
Phase
Comparison
f'H
1/101
fH
1/525
Field
1
Synthesizer
HRI 23
VRI
1
17 27 8 12 4 6 3 7 5 2
∗ Internal inverter is usable as VCO.
• SECAM
14.187MHz ( = 908fH)
4fscIN
10
25
CLOUT
26
CLIN
9
VDD
14 28
VSS
VDD
Synthesizer
10k
22
MODE2
HRI
23
VRI 1
17 27 8 12 4 6 3 7 5 2
∗ COLB is output to BF/COLB OUT pin.
∗ SDR and SDB are formed in PLL using 908fH.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 11 –
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CXD1217.PDF ] | |
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