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PDF CXB1455R Data sheet ( Hoja de datos )
| Número de pieza | CXB1455R | |
| Descripción | VGA/SVGA/XGA 24-bit Transmitter | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXB1455R
VGA/SVGA/XGA 24-bit Transmitter
Description
The CXB1455R is the IC which transmits the 24-bit
VGA/SVGA/XGA definition moving picture based on
the GVIF (Gigabit Video Interface) technology.
48 pin LQFP (Plastic)
Features
• 1 chip transmitter for serial transmission of 24-bit
color VGA/SVGA/XGA picture
• On-chip PLL synthesizer
• On-chip differential cable driver
• TTL/CMOS compatible interface
• Supports 1 pixel/shift clock mode with 1 chip and
2 pixel/shift clock mode with 2 chips
• Single 3.3V power supply
• Low power consumption
• 48-pin plastic QFP package (7mm × 7mm)
Application
Gigabit video interface
Structure
Bi-CMOS IC
Absolute Maximum Ratings
• Power supply
VCC
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
4.2
0 to +85
–65 to +150
V
°C
°C
333 mW
Block Diagram and Pin Configuration
Recommended Operating Condition
Supply voltage
3.3 ± 0.3
V
36 35 34 33 32 31 30 29 28 27 26 25
GND 37
REFREQ 38
CNTL 39
DE 40
PLL
Cable
Driver
SFTCLK 41
HSYNC 42
VSYNC 43
B7 44
P/S
Converter
B6 45
B5 46
B4 47
Encoder
VDD 48
24 VDD
23 R0
22 R1
21 R2
20 R3
19 R4
18 R5
17 R6
16 R7
15 G0
14 G1
13 GND
1 2 3 4 5 6 7 8 9 10 11 12
Fig. 1. Block Diagram and Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98Y03B03
1 page  
CXB1455R
Table 4. AC Characteristics (Under the recommended operating conditions. See Table 2.)
Item Symbol Min. Typ. Max. Unit
Conditions
TTL input rise time
Tir 0.7
5.0 ns 0.8 to 2.0V
TTL input fall time
Tif 0.7
5.0 ns 2.0 to 0.8V
Minimum SFTCLK frequency
Maximum SFTCLK frequency
Fsftclk
65.0
25.0 MHz
MHz
SFTCLK duty factor
Dsftclk 40
60 % Vth = 1.4V
Pixel/Sync/Cntl setup time to
SFTCLK
Tsetup
2.5
ns
Pixel/Sync/Cntl hold time to
SFTCLK
Thold
2.5
ns
SDATA rise time
SDATA fall time
Tor 200 ps
20 to 80%, CL = 2pF See Fig. 2.
Tof 200 ps
Clock mode assert time
TAclk
50 ns
Clock mode deassert time
TDclk
10
ns
Idle mode assert time
TAidle
150
ns
Idle mode deassert time
TDidle
100
ns
PLL lock-in time
Tlockin
0.1
ms
TTL clock
VCC
VCC/A
51
41
CXB1455R
30
RGB, CE
31
VS, HS, DE, CNTL, CKPOL
GND/A/T
51
FET probe
100
Sampling
oscillo-
scope
Fig. 2. SDATA waveform measurement
–5–
5 Page 
CXB1455R
Recommended Printed Board Structure
L1: Cu plate (18µm) + solder coat
I1: Fiber-glass epoxy core (0.3mm)
L2: Cu plate (36µm)
I2: Fiber-glass epoxy core (0.8mm)
L3: Cu plate (36µm)
I3: Fiber-glass epoxy core (0.3mm)
L4: Cu plate (18µm) + solder coat
Recommended Printed Circuit Board Pattern
Example of power supply and special signal routing
0.5mm
L2 doesn't have the plane
in this area.
EE
A
E
G
A : Through hole to the GNDA plane (L2)
G : Through hole to the GND plane (L2)
E : Through hole to the VccA plane (L3)
T : Through hole to the Vcc plane (L3)
R : Through hole to the REXT resistor (L4)
P : Through hole to the CKPOL signal (L4)
C : Through hole to the CE signal (L4)
Chip capacitor
Chip resistor
G
37 37 GND
REFREQ
CNTL
DE
SFTCLK
HSYNC
VSYNC
BLU <7>
BLU <6>
BLU <5>
BLU <4>
48 48 VCC
RG
PC
TTT
VCC
RED <0>
RED <1>
RED <2>
RED <3>
RED <4>
RED <5>
RED <6>
RED <7>
GRN <0>
GRN <1>
GND
G
24
13 Locate the bypass capacitor
(0.1µF chip capacitor) as close
to the pins as possible.
G
1 12
Microstrip Line
The microstrip line with the characteristic impedance of 50Ω should be used to connect the LSI transmission
signal pin SDATAP/N to the connector foot printer as GVIF transmits the high-speed digital signal with the
maximum speed of 2Gb/s. The optimal line can be made by forming 0.5mm pattern on L1. (See the board
structure shown below.) The line lengths should be the same and the through hole should be not used.
Normally, L2 should be the mat GND.
Termination Elements
Locate the 51Ω termination resistors as close to the LSI as possible.
Filter Device and Reference Resistor
The capacitor and resistor connected to LPFA/B and REXT are the filter and the reference resistor. Locate
them as close to the LSI as possible. Decrease the parasitic capacitance by removing the L2 GND plane
under these elements and wiring.
– 11 –
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CXB1455R.PDF ] | |
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