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PDF CY7C342B-15JC Data sheet ( Hoja de datos )
| Número de pieza | CY7C342B-15JC | |
| Descripción | 128-Macrocell MAX EPLDs | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
128-Macrocell MAX® EPLD
Features
• 128 macrocells in eight logic array blocks (LABs)
• Eight dedicated inputs, 52 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 68-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
The 128 macrocells in the CY7C342B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C342B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 25 times the functionality of 20-pin PLDs,
the CY7C342B allows the replacement of over 50 TTL devices.
By replacing large amounts of logic, the CY7C342B reduces board
space, part count, and increases system reliability.
Logic Block Diagram
1 (B6) INPUT/CLK
2 (A6)
INPUT
32 (L4)
INPUT
34 (L5)
INPUT
INPUT
INPUT
INPUT
INPUT
(A7) 68
(A8) 66
(L6) 36
(K6) 35
4 (A5)
5 (B4)
6 (A4)
7 (B3)
8 (A3)
9 (A2)
10 (B2)
11 (B1)
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17 (E1)
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 9–16
LAB B
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22–32
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38–48
SYSTEM CLOCK
P
I
A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121–128
LAB G
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 102–112
LAB F
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 86–96
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)
LAB D
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
MACROCELL 57–64
3, 20, 37, 54 (B5, G2, K7, E10)
16, 33, 50, 67 (E2, K5, G10, B7)
VCC
GND
LAB E
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 73–80
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
() – PERTAIN TO 68-PIN PGA PACKAGE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03014 Rev. *B
Revised April 22, 2004
1 page  
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C342B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to +135°C
Ambient Temperature with
Power Applied............................................ –65°C to +135°C
Maximum Junction Temperature
(under bias).................................................................. 150°C
Supply Voltage to Ground Potential ............–2.0V to +7.0V[1]
DC Output Current per Pin[1] ................... –25 mA to +25 mA
DC Input Voltage[1] .........................................–2.0V to +7.0V
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 5%
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
VCC
VOH
VOL
VIH
VIL
IIX
IOZ
tR
tF
Description
Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Current
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
Test Conditions
Maximum VCC rise time is 10 ms
IOH = –4 mA DC[2]
IOL = 8 mA DC[2]
VI = VCC or ground
VO = VCC or ground
Min.
4.75(4.5)
2.4
2.0
–0.3
–10
–40
Max.
5.25(5.5)
0.45
VCC + 0.3
0.8
+10
+40
100
100
Unit
V
V
V
V
V
µA
µA
ns
ns
Capacitance
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
10
20
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
R1 464Ω
5V
OUTPUT
R1 464Ω
50 pF
INCLUDING
JIG AND
SCOPE
R2
250Ω
(a)
5 pF
R2
250Ω
INCLUDING
JIG AND
SCOPE
(b)
3.0V
10%
GND
≤ 6 ns
ALL INPUT PULSES
90%
90%
10%
≤ 6 ns
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
OUTPUT
163Ω
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Document #: 38-03014 Rev. *B
Page 5 of 14
5 Page 
Package Diagrams
USE ULTRA37000TM FOR
ALL NEW DESIGNS
68-pin Windowed Leaded Chip Carrier H81
CY7C342B
Document #: 38-03014 Rev. *B
51-80080-**
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C342B-15JC.PDF ] | |
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