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PDF CY7C277-50PC Data sheet ( Hoja de datos )
| Número de pieza | CY7C277-50PC | |
| Descripción | 32K x 8 Reprogrammable Registered PROM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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77
CY7C277
32K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 30-ns address set-up
— 15-ns clock to output
• Low power
— 60 mW (commercial)
— 715 mW (military)
• Programmable address latch enable input
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered output registers
• EPROM technology, 100% programmable
• Slim 300-mil, 28-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static dis-
charge
Logic Block Diagram
A14
A13 X
A12
A11
ADDRESS
ROW
DECODER
256 x 1024
PROGRAMMABLE
8-BIT
1 OF 128
A10
1 OF 256
ARRAY
MUX
A9
A8 15-BIT
A7 ADDRESS
A6
TRANSPARENT/
LATCH
A5
A4
A3 Y
A2 ADDRESS
A1
A0 ALE
COLUMN
DECODER
1 OF 32
PROGRAMMABLE
CP/ALE OPTIONS
ALE
8-BIT
EDGE-
TRIGGERED
REGISTER
CP
E/E S
CP
PROGRAMMABLE
D Q MULTIPLEXER
C
O7
O6
O5
O4
O3
O2
O1
O0
Pin Configurations
DIP/Flatpack
Top View
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A10
26 A11
25 A12
24 A13
23 A14
22 ALE
21 CP
20 E/ES
19 O7
18 O6
17 O5
16 O4
15 O3
LCC/PLCC (Opaque Only)
Top View
4 3 2 1 32 31 30
A6
A5
A4
A3
A2
A1
A0
5
6
7
8
9
10
11
29 A12
28 A13
27 A14
26 NC
25 ALE
24 CP
23 E/ES
NC 12
22 O7
O0 13
21 O6
14151617 181920
Selection Guide
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
Maximum Operating
Current (mA)
Com’l
Mil
7C277-30
30
15
120
7C277-40
40
20
120
130
7C277-50
50
25
120
130
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04006 Rev. **
Revised March 4, 2002
1 page  
CY7C277
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
Table 1. Mode Selection
Read or Output Disable
Mode
Other
Read
Output Disable
Program
Program Verify
Program Inhibit
Blank Check
Note:
10. X = “don’t care” but not to exceed VCC ±5%.
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
A14–A0
E, ES
VFY
VIL
VIH
VIHP
VILP
VIHP
VILP
Pin Function[10]
CP
PGM
VIH
X
VILP
VIHP/VILP
VIHP
VIHP/VILP
ALE
VPP
VIL
X
VPP
VPP
VPP
VPP
O7–O0
D7–D0
O7–O0
High Z
D7–D0
O7–O0
High Z
O7–O0
DIP
Top View
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A10
26 A11
25 A12
24 A13
23 A14
22 VPP
21 PGM
20 VFY
19 D7
18 D6
17 D5
16 D4
15 D3
LCC/PLCC (Opaque Only)
Top View
4 3 2 1 32 31 30
A6 5
A5
A4
A3
A2
A1
A0
6
7
8
9
10
11
29 A12
28 A13
27 A14
26 NC
25 VPP
24 PGM
23 VFY
NC 12
22 D7
D0 13
21 D6
14151617 181920
Figure 1. Programming Pinouts
Document #: 38-04006 Rev. **
Page 5 of 13
5 Page 
Package Diagrams (continued)
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
CY7C277
51-80103-*A
Document #: 38-04006 Rev. **
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY7C277-50PC.PDF ] | |
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