PDF CY7C274-35QMB Data sheet ( Hoja de datos )

Número de pieza	CY7C274-35QMB
Descripción	32K x 8 Power Switched and Reprogrammable PROM
Fabricantes	Cypress Semiconductor
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No Preview Available ! 1CY7C274 CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed — 30 ns (Commercial) — 35 ns (Military) • Low power — 660 mW (commercial) — 715 mW (military) • Super low standby power — Less than 165 mW when deselected • EPROM technology 100% programmable • Slim 300-mil package (7C271) • Direct replacement for bipolar PROMs • Capable of withstanding >2001V static discharge Functional Description The CY7C271 and CY7C274 are high-performance 32,768-word by 8-bit CMOS PROMs. When disabled (CE HIGH), the 7C271/7C274 automatically powers down into a low-power stand-by mode. The CY7C271 is packaged in the 300-mil slim package. The CY7C274 is packaged in the industry standard 600-mil package. Both the CY7C271 and CY7C274 are available in a cerDIP package equipped with an erasure window to provide for reprogrammability. When exposed to UV light, the PROM is erased and can be repro- grammed. The memory cells utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms. The CY7C271 and CY7C274 offer the advantage of lower power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the super voltage, and low current requirements allow for gang programming. The EPROM cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming, the product will meet DC and AC specification limits. Reading the 7C271 is accomplished by placing active LOW signals on CS1 and CE, and an active HIGH on CS2. Reading the 7C274 is accomplished by placing active LOW signals on OE and CE. The contents of the memory location addressed by the address lines (A0−A14) will become available on the output lines (O0−O7). Logic Block Diagram A14 A13 A12 X ADDRESS A11 A10 256 x 1024 PROGRAMABLE ARRAY 8 x 1 OF 128 MULTIPLEXER A9 A8 A7 A6 A5 A4 A3 Y ADDRESS A2 A1 A0 POWER-DOWN CE (7C271) CS1 (7C271) CS2 (7C274) OE Pin Configurations DIP/Flatpack O7 A9 1 28 VCC A8 2 27 A10 A7 3 26 A11 O6 A6 4 25 A12 A5 5 24 A13 A4 6 7C271 23 A14 O5 A3 7 22 CS1 A2 8 21 CS2 A1 9 20 CE O4 A0 10 O0 11 19 O7 18 O6 O1 12 17 O5 O2 13 16 O4 O3 GND 14 15 O3 DIP/Flatpack VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 28 2 27 3 26 4 25 5 24 6 7C274 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 LCC/PLCC (Opaque Only) LCC/PLCC (Opaque Only) O2 4 3 2 1 32 31 30 4 3 2 1 32 31 30 O1 A6 5 A5 6 A4 7 7C271 29 A12 28 A13 27 A14 A6 5 A5 6 A4 7 7C274 29 A8 28 A9 27 A11 A3 8 26 NC A3 8 26 NC O0 A2 9 A1 10 25 CS1 24 CS2 A2 9 A1 10 25 OE 24 A10 A0 11 23 CE A0 11 23 CE NC 12 22 O7 NC 12 22 O7 O0 13 21 O6 O0 13 21 O6 14151617 181920 14151617 181920 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-04008 Rev. B Revised December 27, 2002 1 page CY7C271 CY7C274 Table 2. CY7C274 Mode Selection Read or Output Disable Mode Other Read Output Disable Power Down Program Program Verify Program Inhibit Blank Check Note: 8. X can be VIL (VILP) or VIH (VIHP). 9. VPP should be tied to VCC ±5% in read mode. A14–A0 A14–A0 A14–A0 A14–A0 A14–A0 A14–A0 A14–A0 A14–A0 A14–A0 OE VFY VIL VIH X VIHP VILP VIHP VILP Pin Function[8] CE PGM VIL X VIH VILP VIHP/VILP VIHP VIHP/VILP VPP VPP Note 9 X X VPP VPP VPP VPP DIP Top View A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 28 2 27 3 26 4 25 5 7C271 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A10 A11 A12 A13 A14 VPP PGM VFY D7 D6 D5 D4 D3 LCC Top View 4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC 5 6 7 8 9 10 11 12 7C271 29 A12 28 A13 27 A14 26 NC 25 VPP 24 PGM 23 VFY 22 D7 D0 13 21 D6 14151617 181920 DIP Top View VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 28 2 27 3 26 4 25 5 7C274 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A14 A13 A8 A9 A11 VFY A10 PGM D7 D6 D5 D4 D3 LCC Top View 4 3 2 1 32 31 30 A6 5 A5 A4 A3 A2 A1 A0 NC 6 7 8 9 10 11 12 7C274 29 A8 28 A9 27 A11 26 NC 25 VFY 24 A10 23 PGM 22 D7 D0 13 21 D6 14151617 181920 Figure 1. Programming Pinouts O7–O0 D7–D0 O7–O0 High Z High Z D7–D0 O7–O0 High Z O7–O0 Document #: 38-04008 Rev. B Page 5 of 11 5 Page CY7C271 CY7C274 Document History Page Document Title: CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Document Number: 38-04008 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113864 3/8/02 DSG Change from Spec number: 38-00068 to 38-04008 A* 118899 10/10/02 GBI Updating Ordering Information B 122249 12/27/02 RBI Add power up requirements to Operating Conditions information Document #: 38-04008 Rev. B Page 11 of 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C274-35QMB	32K x 8 Power Switched and Reprogrammable PROM	Cypress Semiconductor

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