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PDF CY7C1484V33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1484V33 | |
| Descripción | 2M x 36/4M x 18 Pipelined DCD SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C1484V33
CY7C1485V33
2M x 36/4M x 18 Pipelined DCD SRAM
Features
• Fast clock speed: 250, 200, and 167 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast access time: 2.6, 3.0, and 3.4 ns
• Optimal for depth expansion
• Single 3.3V –5% and +5% power supply VDD
• Separate VDDQ for 3.3V or 2.5V
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages (CY7C1484V33 and CY7C1485V33).
• 165-ball FBGA will be offered on an opportunity basis.
(Please contact Cypress sales or marketing)
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1484V33 and CY7C1485V33 SRAMs integrate
2,097,152 × 36/4,194,304 × 18 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
CY7C1484V33-
250
CY7C1485V33-
250
2.6
TBD
TBD
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control
inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQx) and the data
parity (DPx) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1484V33 and DQa,b
and DPa,b apply to CY7C1485V33. a, b, c, and d each are
eight bits wide in the case of DQ and one bit wide in the case
of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPd. BWd controls DQ and DPd. BWa, BWb,
BWc, BWd can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. Write pass-through
capability allows written data available at the output for the
immediately next Read cycle. This device also incorporates
pipelined enable circuit for easy depth expansion without
penalizing system performance.
The CY7C1484V33/CY7C1485V33 are both double-cycle
deselect parts.All inputs and outputs of the CY7C1484V33,
CY7C1485V33 are JEDEC standard JESD8-5-compatible.
CY7C1484V33-
200
CY7C1485V33-
200
3.0
TBD
TBD
CY7C1484V33-
167
CY7C1485V33-
167
3.4
TBD
TBD
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05285 Rev. *A
Revised January 18, 2003
1 page  
PRELIMINARY
CY7C1484V33
CY7C1485V33
Pin Configurations (continued)
165-ball Bump FBGA (This package is offered on an opportunity basis)
CY7C1484V33 (2M × 36)–11 × 15 FBGA
12
A NC
A
B NC
C DPc
A
NC
D DQc DQc
E DQc DQc
F DQc DQc
G DQc DQc
H NC
VSS
J DQd DQd
K DQd DQd
L DQd DQd
M DQd DQd
N DPd
NC
P NC
A
R MODE
A
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
144M
DPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DPa
A
A
CY7C1485V33 (4M × 18)–11 × 15 FBGA
12
A NC
A
B NC
A
C NC
NC
D NC DQb
E NC DQb
F NC DQb
G NC DQb
H NC
J DQb
VSS
NC
K DQb
L DQb
NC
NC
M DQb
NC
N DPb
NC
P NC
A
R MODE
A
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
NC
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
A0
7
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDO
TCK
8
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
144M
DPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Pin Definitions
Pin Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and
BWE).
Document #: 38-05285 Rev. *A
Page 5 of 29
5 Page 
PRELIMINARY
CY7C1484V33
CY7C1485V33
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
When the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (TCS and TCH). The SRAM clock input might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05285 Rev. *A
Page 11 of 29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet CY7C1484V33.PDF ] | |
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