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PDF CY7C4271 Data sheet ( Hoja de datos )
| Número de pieza | CY7C4271 | |
| Descripción | 16K/32K x 9 Deep Sync FIFOs | |
| Fabricantes | Cypress Semiconductor | |
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CY7C4261, CY7C4271
16 K/32 K × 9 Deep Sync FIFOs
16K/32 K × 9 Deep Sync FIFOs
Features
■ High speed, low power, first-in first-out (FIFO) memories
■ 16 K × 9 (CY7C4261)
■ 32 K × 9 (CY7C4271)
■ 0.5 micron CMOS for optimum speed and power
■ High speed 100 MHz operation (10 ns read/write cycle times)
■ Low power — ICC = 35 mA
■ Fully asynchronous and simultaneous read and write operation
■ Empty, full, half full, and programmable almost empty and
almost full status flags
■ TTL compatible
■ Output enable (OE) pins
■ Independent read and write enable pins
■ Center power and ground pins for reduced noise
■ Supports free running 50% duty cycle clock inputs
■ Width expansion capability
■ 32-pin PLCC and 32-pin TQFP
■ Pin compatible density upgrade to CY7C42X1 family
■ Pin compatible density upgrade to IDT72201/11/21/31/41/51
■ Pb-free packages available
Functional Description
The CY7C4261/71 are high speed, low power FIFO memories
with clocked read and write interfaces. All are nine bits wide. The
CY7C4261/71 are pin compatible to the CY7C42X1
synchronous FIFO family. The CY7C4261/71 can be cascaded
to increase FIFO width. Programmable features include
almost full/almost empty flags. These FIFOs provide solutions
for a wide variety of data buffering needs, including high speed
data acquisition, multiprocessor interfaces, and communications
buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a free running read clock (RCLK) and two read enable
pins (REN1, REN2). In addition, the CY7C4261/71 has an output
enable pin (OE). The read (RCLK) and write (WCLK) clocks may
be tied together for single-clock operation or the two clocks may
be run independently for asynchronous read/write applications.
Clock frequencies up to 100 MHz are achievable. Depth
expansion is possible using one enable input for system control,
while the other enable is controlled by expansion logic to direct
the flow of data.
For a complete list of related documentation, click here.
Selection Guide
Parameter
Maximum frequency
Maximum access time
Minimum cycle time
Minimum data or enable setup
Minimum data or enable hold
Maximum flag delay
Active power supply current (ICC1)
Commercial
Industrial
Density
Package
Parameter
7C4261-10
100
8
10
3
0.5
8
35
40
CY7C4261
16 K × 9
32-pin PLCC
7C4271-15
66.7
10
15
4
1
10
35
40
Unit
MHz
ns
ns
ns
ns
ns
mA
CY7C4271
32 K × 9
32-pin TQFP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06015 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014
1 page  
CY7C4261, CY7C4271
Functional Description
The CY7C4261/71 provides four status pins: empty, full,
programmable almost empty, and programmable almost full. The
almost empty/almost full flags are programmable to single word
granularity. The programmable flags default to empty + 7 and
full – 7.
The flags are synchronous, that is, they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the empty and almost empty states, the flags
are updated exclusively by the RCLK. The flags denoting almost
full, and full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using an advanced 0.5 CMOS
technology. Input ESD protection is greater than 2001 V, and
latch-up is prevented by the use of guard rings.
Architecture
The CY7C4261/71 consists of an array of 16 K to 32 K words of
nine bits each (implemented by a dual port array of SRAM cells),
a read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power up, the FIFO must be reset with a reset (RS) cycle.
This causes the FIFO to enter the empty condition signified by
EF being LOW. All
rising edge of RS.
data outputs
For the FIFO
(tQo 0re8s)egt otoLiOtsWdetRfaSuFltasftteartet,hae
falling edge must occur on RS and the user must not read or write
while RS is LOW. All flags are guaranteed to be valid tRSF after
RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH,
and
into
FF
the
is active
FIFO on
HIGH, data present on
each rising edge of the
WtheCLDK0 s8igpninasl.
is written
Similarly,
when the REN1 and REN2 signals are active LOW and EF is
active HIGH, data in the FIFO memory is presented on the Q08
outputs. New data is presented on each rising edge of RCLK
while REN1 and REN2 are active. REN1 and REN2 must set up
tENS before RCLK for it to be a valid read function. WEN1 and
WEN2 must occur tENS before WCLK for it to be a valid write
function.
An output enable
outputs when OE
(OE) pin is
is asserted.
provided
When OE
to
is
three-state the
enabled (LOW),
Qda0ta8
in the output register is
devices are cascaded,
available to the
the OE function
Qon0ly8
outputs
outputs
after tOE. If
data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q08 outputs even
after additional reads occur.
Write enable 1 (WEN1). If the FIFO is configured for
programmable flags, write enable 1 (WEN1) is the only write
enable control pin. In this configuration, when write enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write enable 2/load (WEN2/LD). This is a dual purpose pin. The
FIFO is configured at reset to have programmable flags or to
have two write enables, which allows for depth expansion. If
write enable 2/load (WEN2/LD) is set active HIGH at reset
(RS = LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when write
enable (WEN1) is LOW and write enable 2/load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM array
on the LOW-to-HIGH transition of every write clock (WCLK).
Data is stored in the RAM array sequentially and independently
of any ongoing read operation.
Programming
When WEN2/LD is held LOW during reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C4261/71 for writing or reading data to
these registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again. Figure 3 shows the register sizes and default
values for the various device types.
Figure 3. Offset Register Location and Default Values
16K × 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
32K × 9
87
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
5
08
6
0
(MSB)
000000
(MSB)
0000000
87
0
Full Offset (LSB) Reg
Default Value = 007h
87
0
Full Offset (LSB) Reg
Default Value = 007h
8
5
08
6
0
(MSB)
000000
(MSB)
0000000
Document Number: 38-06015 Rev. *I
Page 5 of 21
5 Page 
CY7C4261, CY7C4271
Switching Waveforms (continued)
RS
REN1,
REN2
Figure 8. Reset Timing [16]
tRS
tRSS
tRSR
tRSS
tRSR
WEN1
WEN2/LD [18]
tRSS
tRSR
EF,PAE
FF,PAF
Q0 - Q8
tRSF
tRSF
tRSF
Figure 9. First Data Word Latency after Reset with Read and Write
WCLK
D0 –D8
WEN1
tDS
tENS
D0(FIRST VALID WRITE)
tFRL [19]
D1
D2 D3
WEN2
(if applicable)
RCLK
EF
REN1,
REN2
tSKEW1
tREF
tA [20]
tA
OE = 1[17]
OE = 0
D4
Q0 –Q8
OE
tOLZ
tOE
D0 D1
Notes
16. The clocks (RCLK, WCLK) can be free running during reset.
17. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.
18. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the
programmable flag offset registers.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 × tCLK + tSKEW1 or tCLK +
tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document Number: 38-06015 Rev. *I
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY7C4271.PDF ] | |
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