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PDF DAC56 Data sheet ( Hoja de datos )
| Número de pieza | DAC56 | |
| Descripción | Monolithic 16-Bit Resolution DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DAC56 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
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DAC56
® 49%
FPO
DAC56
DAC56
Monolithic 16-Bit Resolution
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q COMPLETE D/A CONVERTER:
Internal Voltage Reference
±3V Output Operational Amplifier
Pinout Allows IOUT (±1.0mA) Option
No external components required
q 0.012% LINEARITY ERROR MAX
q 12-BIT MONOTONICITY GUARANTEED
OVER 0°C TO +70°C
q ±5V TO ±12V POWER SUPPLY
q SETTLING TIME: VOUT = 1.5µs;
IOUT = 350ns
q SERIAL DATA INPUT: Binary Two’s
Complement
q 16-PIN PLASTIC DIP AND SOIC
DESCRIPTION
The DAC56 is a complete 16-bit monolithic D/A
converter. Completely self-contained with a stable,
low noise, internal zener voltage reference; high-speed
current switches; a resistor ladder network; and a low
noise output operational amplifier all on a single
monolithic chip. The DAC56 operates over a wide
power supply range from ±5V to ±12V.
Differential linearity error (DLE) is guaranteed to
meet specifications without external adjustment. How-
ever, provisions for an externally adjustable circuit
controlling the MSB error, the differential linearity
error at bipolar zero, makes the DLE at BPZ essen-
tially zero and provides for high system performance.
The I/V amplifier stage includes an output current
limiting circuit to protect both amplifier and load from
excessive current. This assures the user of high system
reliability.
APPLICATIONS
q PROCESS CONTROL
q ATE PIN ELECTRONICS LEVEL SETTING
q CLOSED-LOOP SERVO-CONTROL
q AUTO-CALIBRATION CIRCUIT FOR A/D
BOARDS
q UP-GRADE REPLACEMENT FOR
MULTIPLYING D/A
q X-Y PLOTTER
q DSP PROCESSOR BOARDS
A high-speed interface is capable of clocking in data
at a rate of 10MHz max, and its interface logic con-
tains a serial data clock (input), serial data (input) and
latch-enable (input). Serial data is clocked MSB first
into a 16-bit register and then latched into a 16-bit
parallel register.
The DAC56 is packaged in a 16-pin plastic DIP and
16-pin SOIC.
Reference
16-Bit
IOUT DAC
RF
16-Bit Input Latch
Output
16-Bit Serial-to-Parallel Conversion
Clock LE Data
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
PDS-11231A
DAC56
®
1 page  
CLK
(1)
MSB
LSB
DATA (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
MSB
LE (3)
(4)
NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch
enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going
negative.
FIGURE 4. Input Timing Diagram.
DATA
> 40ns
LSB
MSB
CLK
LE
>15ns >15ns
> 40ns
> 40ns
> 100ns
> 5ns
> 15ns
> One Clock Cycle
> One Clock Cycle
FIGURE 5. Input Timing Relationships.
INPUT TIMING CONSIDERATIONS
Figures 4 and 5 refer to the input timing required to interface
the inputs of DAC56 to a serial input data stream. Serial data
is accepted in Binary Two’s Complement with the MSB being
loaded first. Data is clocked in on positive going clock (CLK,
pin 5) edges and is latched into the DAC input register on
negative going latch enable (LE, pin 6) edges.
The latch enable input must be high for at least one clock cycle
before going low, and then must be held low for at least one
clock cycle. The last 16 data bits clocked into the serial input
register are those that are transferred to the DAC input register
when latch enable goes low. In other words, when more than
16 clock cycles occur between a latch enable, only the data
present during the last 16 clocks will be transferred to the
DAC input register.
Figure 4 gives the general input format required for the
DAC56. Figure 5 shows the specific relationships between the
various signals and their timing constraints.
®
5 DAC56
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet DAC56.PDF ] | |
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