PDF DAC1221 Data sheet ( Hoja de datos )

Número de pieza	DAC1221
Descripción	16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® DAC1221 DAC1221 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER FEATURES q 16-BIT MONOTONICITY GUARANTEED OVER –40°C TO +85°C q LOW POWER: 1.2mW q VOLTAGE OUTPUT q SETTLING TIME: 2ms to 0.012% q MAX LINEARITY ERROR: 30ppm q ON-CHIP CALIBRATION DESCRIPTION The DAC1221 is a Digital-to-Analog (D/A) converter offering 16-bit monotonic performance over the speci- fied temperature range. It utilizes delta-sigma technol- ogy to achieve inherently linear performance in a small package at very low power. The output range is two times the external reference voltage. On-chip calibration circuitry dramatically reduces offset and gain errors. APPLICATIONS q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO-CONTROL q SMART TRANSMITTERS q PORTABLE INSTRUMENTS q VCO CONTROL The DAC1221 features a synchronous serial interface. In single converter applications, the serial interface can be accomplished with just two wires, allowing low- cost isolation. For multiple converters, a CS signal allows for selection of the appropriate D/A converter. The DAC1221 has been designed for closed-loop control applications in the industrial process control market, and high resolution applications in the test and measurement market. It is also ideal for remote appli- cations, battery-powered instruments, and isolated sys- tems. The DAC1221 is available in a SSOP-16 package. XIN XOUT VREF C1 C2A C2B C3 Clock Generator Microcontroller Instruction Register Command Register Data Register Offset Register Full-Scale Register SDIO SCLK Serial Interface Second-Order ∆∑ Modulator First-Order Switched Capacitor Filter Second-Order Continuous Time Post Filter Modulator Control VOUT CS DVDD DGND AVDD AGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1519B 1 DAPCrint1ed2in2U1.S.A. May, 2000 ® 1 page TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = DVDD = +3.0V, fXIN = 2.5MHz, VREF = 1.25V, C1 = 2.2nF, C2 = 150pF and C3 = 6.8nF. 0.020 GAIN ERROR vs TEMPERATURE 0.015 0.010 (can be corrected with calibration) 0.005 0.000 –0.005 –0.010 –0.015 –50 –25 0 25 50 Temperature (°C) 75 100 25 20 15 10 5 0 –5 0 LINEARITY ERROR vs CODE 0.2 0.4 0.6 0.8 16-Bit Input Code Normalized 1 ® 5 DAC1221 5 Page I/O Recovery If serial communication stops during an instruction or data transfer for longer than 100ms (for fXIN = 2.5MHz), the DAC1221 will reset its serial interface. This will not affect the internal registers. The main controller must not continue the transfer after this event, but must restart the transfer from the beginning. This feature is very useful if the main control- ler can be reset at any point. After reset, simply wait 200ms (for fXIN = 2.5MHz) before starting serial communication. Isolation The serial interface of the DAC1221 provides for simple isolation methods. An example of an isolated two-wire interface is shown in Figure 4. Using CS The serial interface may make use of the CS signal, or this input may simply be tied LOW. There are several issues associated with choosing to do one or the other. The CS signal does not directly control the tri-state condition of the SDIO output. These signals are normally in the tri-state condition. They only become active when serial data is being transmitted from the DAC1221. If the DAC1221 is in the middle of a serial transfer and the SDIO is an output, taking CS HIGH will not tri-state the output signal. If there are multiple serial peripherals utilizing the same serial I/O lines and communication may occur with any peripheral at any time, the CS signal must be used. The CS signal is then used to enable communication with the DAC1221. TIMING The maximum serial clock frequency cannot exceed the DAC1221 XIN frequency divided by 10. Table VIII and Figures 5 through 9 define the basic digital timing character- istics of the DAC1221. Figure 5 and the associated timing symbols apply to the XIN input signal. Figures 6 through 9 and associated timing symbols apply to the serial interface signals (SCLK, SDIO, and CS). The serial interface is discussed in detail in the Serial Interface section. SCLK t2 t1 t3 FIGURE 3. Resetting the DAC1221. Reset On t1: > 512 • tXIN < 800 • tXIN Falling Edge t2: > 10 • tXIN t2 t3: > 1024 • tXIN < 1800 • tXIN t4 t4: ≥ 2048 • tXIN < 2400 • tXIN C1X 5.6pF C2X 5.6pF DVDD XTAL AVDD DAC1221 1 DVDD SCLK 16 2 XOUT SDIO 15 3 XIN CS 14 4 DGND AGND 13 5 AVDD 6 DNC 7 C3 8 C2B VREF 12 VOUT 11 C2A 10 C1 9 Isolated Power Opto Coupler Opto Coupler C1 C2 VREF C3 P1.1 8051 P1.0 = Isolated = DGND = AGND FIGURE 4. Isolation for Two-Wire Interface. 11 DAC1221 ® 11 Page

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