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DAC1208 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DAC1208
Beschreibung 12-Bit/ uP Compatible/ Double-Buffered D to A Converters
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 18 Seiten
DAC1208 Datasheet, Funktion
February 1995
MICRO-DACTM DAC1208 DAC1209 DAC1210 DAC1230
DAC1231 DAC1232 12-Bit mP Compatible
Double-Buffered D to A Converters
General Description
The DAC1208 and the DAC1230 series are 12-bit multiply-
ing D to A converters designed to interface directly with a
wide variety of microprocessors (8080 8048 8085 Z-80
etc ) Double buffering input registers and associated con-
trol lines allow these DACs to appear as a two-byte ‘‘stack’’
in the system’s memory or I O space with no additional in-
terfacing logic required
The DAC1208 series provides all 12 input lines to allow sin-
gle buffering for maximum throughput when used with 16-bit
processors These input lines can also be externally config-
ured to permit an 8-bit data interface The DAC1230 series
can be used with an 8-bit data bus directly as it internally
formulates the 12-bit DAC data from its 8 input lines All of
these DACs accept left-justified data from the processor
The analog section is a precision silicon-chromium (Si-Cr)
R-2R ladder network and twelve CMOS current switches
An inverted R-2R ladder structure is used with the binary
weighted currents switched between the IOUT1 and IOUT2
maintaining a constant current in each ladder leg indepen-
dent of the switch state Special circuitry provides TTL logic
input voltage level compatibility
The DAC1208 series and DAC1230 series are the 12-bit
members of a family of microprocessor compatible DACs
(MICRO-DACsTM) For applications requiring other resolu-
tions the DAC1000 series for 10-bit and DAC0830 series
for 8-bit are available alternatives
Features
Y Linearity specified with zero and full-scale adjust only
Y Direct interface to all popular microprocessors
Y Double-buffered single-buffered or flow through digital
data inputs
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant
multiplication
Y Operates stand-alone (without mP) if desired
Y All parts guaranteed 12-bit monotonic
Y DAC1230 series is pin compatible with the DAC0830
series 8-bit MICRO-DACs
Key Specifications
Y Current Settling Time
Y Resolution
Y Linearity (Guaranteed
over temperature)
Y Gain Tempco
Y Low Power Dissipation
Y Single Power Supply
1 ms
12 Bits
10 11 or 12 Bits of FS
1 3 ppm C
20 mW
5 VDC to 15 VDC
Typical Application
TRI-STATE is a registered trademark of National Semiconductor Corp
MICRO-DACTM is a trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL H 5690
TL H 5690 – 1
RRD-B30M115 Printed in U S A






DAC1208 Datasheet, Funktion
Application Hints
1 0 DIGITAL INTERFACE
These DACs are designed to provide all of the necessary
digital input circuitry to permit a direct interface to a wide
variety of microprocessor systems The timing and logic lev-
el convention of the input control signals allow the DACs to
be treated as a typical memory device or I O peripheral with
no external logic required in most systems Essentially
these DACs can be mapped as a two-byte stack in memory
(or I O space) to receive their 12 bits of input data in two
successive 8-bit data writing sequences The DAC1230 se-
ries is intended for use in systems with an 8-bit data bus
The DAC1208 series provides all 12 digital input lines which
can be externally configured to be controlled from an 8-bit
bus or can be driven directly from a 16-bit data bus
All of the digital inputs to these DACs contain a unique
threshold regulator circuit to maintain TTL voltage level
compatibility independent of the applied VCC to the DAC
Any input can also be driven from higher voltage CMOS
logic levels in non-microprocessor based systems To pre-
vent damage to the chip from static discharge all unused
digital inputs should be tied to VCC or ground As a trouble-
shooting aid if any digital input is inadvertently left floating
the DAC will interpret the pin as a logic ‘‘1’’
Double buffered digital inputs allow the DAC to internally
format the 12-bit word used to set the current switching R-
2R ladder network (see section 2 0) from two 8-bit data
write cycles Figures 1 and 2 show the internal data regis-
ters and their controlling logic circuitry The timing diagrams
for updating the DAC output are shown in sections 1 1 1 2
and 1 3 for three possible control modes The method used
depends strictly upon the particular application
FIGURE 1 DAC1208 DAC1209 DAC1210 Functional Diagram
FIGURE 2 DAC1230 DAC1231 DAC1232 Functional Diagram
6
TL H 5690 – 6

6 Page









DAC1208 pdf, datenblatt
Application Hints (Continued)
2 0 ANALOG APPLICATIONS
The analog output signal for these DACs is derived from a
conventional R-2R current switching ladder network A de-
tailed description of this network can be found on the
DAC1000 series data sheet Basically output IOUT1 pro-
vides a current directly proportional to the product of the
applied reference voltage and the digital input word A sec-
ond output IOUT2 will be a current proportional to the com-
plement of the digital input Specifically
IOUT1
e
VREF
R
c
D
4096
IOUT2
e
VREF
R
c
4095 b
4096
D
where D is the decimal equivalent of the applied 12-bit bina-
ry word (ranging from 0 to 4095) VREF is the voltage ap-
plied to the VREF terminal and R is the internal resistance of
the R-2R ladder R is nominally 15 kX
2 1 Obtaining a Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code it is important that the voltages at both
of the current output pins be as near ground potential (0
VDC) as possible With VREFe a10V every millivolt appear-
ing at either IOUT1 or IOUT2 will cause a 0 01% linearity
error In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 9
The inverting input of the op amp is a virtual ground created
by the feedback from its output through the internal 15 kX
resistor RFb All of the output current (determined by the
digital input and the reference voltage) will flow through RFb
to the output of the amplifier Two-quadrant operation can
be obtained by reversing the polarity of VREF thus causing
IOUT1 to flow into the DAC and be sourced from the output
of the amplifier The output voltage in either case is always
equal to IOUT1cRFb and is the opposite polarity of the ref-
erence voltage
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from b10V to a10V
The DAC can be thought of as a digitally controlled attenua-
tor the output voltage is always less than the applied refer-
ence voltage The VREF terminal of the device presents a
nominal impedance of 15 kX to ground to external circuitry
Always use the internal RFb resistor to create an output
voltage since this resistor matches (and tracks with temper-
ature) the value of the resistors used to generate the output
current (IOUT1)
The selected op amp should have as low a value of input
bias current as possible The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage appli-
cations BI-FETTM op amps are highly recommended for use
with these DACs because of their very low input current
VOUT e b(IOUT1 c RFb)
e bVREF(D)
4096
for 0 s D s 4095
FIGURE 9 Unipolar Output Configuration
TL H 5690 – 15
BI-FETTM is a trademark of National Semiconductor Corp
12

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SeitenGesamt 18 Seiten
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