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PDF DAC1007LCN Data sheet ( Hoja de datos )
| Número de pieza | DAC1007LCN | |
| Descripción | P Compatible/ Double-Buffered D to A Converters | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1995
DAC1006 DAC1007 DAC1008 mP Compatible
Double-Buffered D to A Converters
General Description
The DAC1006 7 8 are advanced CMOS Si-Cr 10- 9- and
8-bit accurate multiplying DACs which are designed to inter-
face directly with the 8080 8048 8085 Z-80 and other pop-
ular microprocessors These DACs appear as a memory lo-
cation or an I O port to the mP and no interfacing logic is
needed
These devices combined with an external amplifier and
voltage reference can be used as standard D A converters
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control
All of these DACs are double buffered They can load all 10
bits or two 8-bit bytes and the data format is left justified
The analog section of these DACs is essentially the same
as that of the DAC1020
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DACTM’s) For
applications requiring other resolutions the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives
Part
Accuracy Pin Description
(bits)
DAC1006
DAC1007
DAC1008
10
9
8
For left-
20 justified
data
MICRO-DACTM and BI-FETTM are trademarks of National Semiconductor Corp
Features
Y Uses easy to adjust END POINT specs NOT BEST
STRAIGHT LINE FIT
Y Low power consumption
Y Direct interface to all popular microprocessors
Y Integrated thin film on CMOS structure
Y Double-buffered single-buffered or flow through digital
data inputs
Y Loads two 8-bit bytes or a single 10-bit word
Y Logic inputs which meet TTL voltage level specs (1 4V
logic threshold)
Y Works with g10V reference full 4-quadrant multiplica-
tion
Y Operates STAND ALONE (without mP) if desired
Y Available in 0 3 standard 20-pin package
Y Differential non-linearity selection available as special
order
Key Specifications
Y Output Current Settling Time
Y Resolution
Y Linearity
Y Gain Tempco
Y Low Power Dissipation
(including ladder)
Y Single Power Supply
500 ns
10 bits
10 9 and 8 bits
(guaranteed over temp )
b0 0003% of FS C
20 mW
5 to 15 VDC
Typical Application
DAC1006 1007 1008
C1995 National Semiconductor Corporation TL H 5688
NOTE FOR DETAILS OF BUS
CONNECTION SEE SECTION 6 0
TL H 5688 – 1
RRD-B30M115 Printed in U S A
1 page  
Block and Connection Diagrams
DAC1006 1007 1008 (20-Pin Parts)
DAC1006 1007 1008
(20-Pin Parts)
Dual-In-Line Package
TL H 5688 – 28
Top View
DAC1006 1007 1008
See Ordering Information
USE DAC1006 1007 1008
FOR LEFT JUSTIFIED DATA
TL H 5688 – 5
Simple Hookup for a ‘‘Quick Look’’
A TOTAL OF 10
INPUT SWITCHES
1K RESISTORS
TL H 5688 – 7
Notes
1 For VREFeb10 240 VDC the output voltage steps are approximately 10 mV each
2 SW1 is a normally closed switch While SW1 is closed the DAC register is latched and new data
can be loaded into the input latch via the 10 SW2 switches
When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes
5
5 Page 
FIGURE 10 Providing a Bipolar Output Voltage with a Single Op Amp
FIGURE 11 Increasing the Output Voltage Swing
TL H 5688 – 13
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure 11 These added
resistors are used to attenuate the aV voltage The overall
gain AV(b) from the aV terminal to the output of the op
amp determines the most negative output voltage b4(aV)
(when the VREF voltage at the a input of the op amp is
zero) with the component values shown The complete dy-
namic range of VOUT is provided by the gain from the (a)
input of the op amp As the voltage at the VREF pin ranges
from 0V to aV(1023 1024) the output of the op amp will
range from b10 VDC to a10V (1023 1024) when using a
aV voltage of a2 500 VDC The 2 5 VDC reference voltage
can be easily developed by using the LM336 zener which
can be biased through the RFB internal resistor connected
to VCC
5 3 Op Amp VOS Adjust (Zero Adjust) for Current
Switching Mode
Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 VDC (ground) Therefore offset
voltage VOS of the external op amp cannot be tolerated as
every millivolt of VOS will introduce 0 01% of added linearity
error At first this seems unusually sensitive until it becomes
clear the 1 mV is 0 01% of the 10V reference High resolu-
tion converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part To prevent this source of error
the VOS of the op amp has to be initially zeroed This is the
‘‘zero adjust’’ of the DAC calibration sequence and should
be done first
If the VOS is to be adjusted there are a few points to consid-
er Note that no ‘‘dc balancing’’ resistance should be used
in the grounded positive input lead of the op amp This re-
sistance and the input current of the op amp can also create
errors The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applica-
tions The VOS of the op amp should be adjusted with a
digital input of all zeros to force IOUTe0 mA A 1 kX resistor
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the VOS
of the op amp and make the zeroing easier to sense
5 4 Full-Scale Adjust
The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode Tech-
niques are given below for all of the possible application
circuits
5 4 1 Current Switching with Unipolar Output Voltage
After doing a ‘‘zero adjust ’’ set all of the digital input levels
HIGH and adjust the magnitude of VREF for
1023
VOUTeb(ideal VREF) 1024
This completes the DAC calibration
11
11 Page | ||
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| PDF Descargar | [ Datasheet DAC1007LCN.PDF ] | |
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