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DAC08HP Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer DAC08HP
Beschreibung 8-Bit/ High-Speed/ Multiplying D/A Converter (Universal Digital Logic Interface)
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
DAC08HP Datasheet, Funktion
a 8-Bit, High-Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
FEATURES
Fast Settling Output Current: 85 ns
Full-Scale Current Prematched to ؎1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maximum over
Temperature Range
High Output Impedance and Compliance:
–10 V to +18 V
Complementary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: ؎10 ppm/؇C
Wide Power Supply Range: ؎4.5 V to ؎18 V
Low Power Consumption: 33 mW @ ؎5 V
Low Cost
Available in Die Form
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog convert-
ers provide very high-speed performance coupled with low cost
and outstanding applications flexibility.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1 reference
current range. Matching to within 1 LSB between reference and
full-scale currents eliminates the need for full-scale trimming in
most applications. Direct interface to all popular logic families
with full noise immunity is provided by the high swing, adjust-
able threshold logic input.
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential opera-
tion to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to
voltage without the need for an external op amp.
All DAC08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as ± 0.1% over the entire operating
temperature range are available. Device performance is essen-
tially unchanged over the ± 4.5 V to ± 18 V power supply range,
with 33 mW power consumption attainable at ± 5 V supplies.
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/
output versatility are required.
FUNCTIONAL BLOCK DIAGRAM
MSB
V+ VLC B1 B2 B3 B4 B5 B6
13 1 5 6 7 8 9 10
DAC08
14
VREF (+)
BIAS
NETWORK
CURRENT
SWITCHES
15
VREF (–)
REFERENCE
AMPLIFIER
16
COMP
3
V–
B7
11
LSB
B8
12
4 IOUT
2
IOUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






DAC08HP Datasheet, Funktion
DAC08
RIN
0V
TYPICAL VALUES:
RIN = 5k
+VIN = 10V
+VREF
RREF
OPTIONAL RESISTOR
FOR OFFSET INPUTS
14
REQ
200
4
RP
15
16
2
NO CAP
RL
RL
Figure 1. Pulsed Reference Operation
C2
+18V
R1 = 9k
C1 = 0.001F
C2, C3 = 0.01F
C1 R1
16 15 14 13 12 11 10 9
DAC08
1 23 4 5 6 78
C3
18V MIN
Figure 2. Burn-in Circuit
2.5V
1V
0.5V
0.5mA
IOUT
2.5mA
100mV
200ns
REQ 200
RL = 100
CC = 0
200ns/DIVISION
Figure 3. Fast Pulsed Reference Operation
0mA
1.0mA
2.0mA
IOUT
IOUT
(0000|0000)
IREF = 2mA
(1111|1111)
Figure 4. True and Complementary Output Operation
5mV
2.4V
2V
0.4V
0V
8A
0
100mV
50ns/DIVISION
50ns
Figure 5. LSB Switching
2.4V
LOGIC INPUT
0.4V
OUTPUT 1/2LSB
SETTLING 0V
+1/2LSB
1V
ALL BITS SWITCHED ON
10mV
SETTLING TIME FIXTURE
IFS = 2mA, RL = 1k
1/2LSB = 4A
50ns
50ns/DIVISION
Figure 6. Full-Scale Settling Time
–6– REV. B

6 Page









DAC08HP pdf, datenblatt
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
0.840 (21.34)
0.745 (18.92)
16 9 0.280 (7.11)
1 8 0.240 (6.10)
PIN 1
0.060 (1.52)
0.325 (8.25)
0.300 (7.62)
0.210 (5.33)
0.015 (0.38)
MAX
0.130
0.160 (4.06)
(3.30)
0.115 (2.93)
MIN
0.022 (0.558) 0.100
0.014
(0.356)
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
16-Lead SO (R-16A)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00) 16
0.1497 (3.80)
1
9 0.2440 (6.20)
0.2284 (5.80)
8
PIN 1 0.050 (1.27) 0.0688 (1.75)
BSC
0.0532 (1.35)
0.0196
0.0099
((00..5205))؋
45؇
0.0098 (0.25)
0.0040 (0.10)
8؇
0.0192 (0.49) SEATING
0.0138 (0.35) PLANE
0.0099 (0.25) 0؇
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
16-Lead Cerdip (Q-16)
0.005 (0.13) MIN 0.080 (2.03) MAX
16
PIN 1
1
9
0.310 (7.87)
0.220 (5.59)
8
0.840 (21.34) MAX 0.060 (1.52)
0.200 (5.08)
0.015 (0.38)
MAX
0.150
0.200 (5.08)
(3.81)
0.125 (3.18)
MIN
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
15° 0.008 (0.20)
0°
20-Terminal Leadless Chip Carrier (E-20)
0.358 (9.09)
0.342 (8.69)
SQ
TOP
VIEW
0.100 (2.54)
0.064 (1.63)
0.200 (5.08)
0.075 BSC
(1.91)
REF
0.100 (2.54) BSC
0.358
(9.09)
MAX
SQ
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
19
18 20
3
4
1
BOTTOM
VIEW
14
13
8
9
0.015 (0.38)
MIN
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
BSC
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40) 0.150 (3.81)
0.045 (1.14)
BSC
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Replacement of SO-16 with R-16A Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. B

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