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DAC0832LCJ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DAC0832LCJ
Beschreibung 8-Bit P Compatible/ Double-Buffered D to A Converters
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 24 Seiten
DAC0832LCJ Datasheet, Funktion
May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DAC).
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
n Works with ±10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Key Specifications
n Current settling time: 1 µs
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
BI-FETand MICRO-DACare trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation DS005608
DS005608-1
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DAC0832LCJ Datasheet, Funktion
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
ILE:
WR1:
Chip Select (active low). The CS in combination
with ILE will enable WR1.
Input Latch Enable (active high). The ILE in combi-
nation with CS enables WR1.
Write 1. The active low WR1 is used to load the digi-
tal input data bits (DI) into the input latch. The data
in the input latch is latched when WR1 is high. To
update the input latch–CS and WR1 must be low
while ILE is high.
WR2:
Write 2 (active low). This signal, in combination with
XFER, causes the 8-bit data which is available in
the input latch to transfer to the DAC register.
XFER: Transfer control signal (active low). The XFER will
enable WR2.
Other Pin Functions
DI0-DI7:
IOUT1:
Digital Inputs. DI0 is the least significant bit (LSB)
and DI7 is the most significant bit (MSB).
DAC Current Output 1. IOUT1 is a maximum for a
digital code of all 1’s in the DAC register, and is
zero for all 0’s in DAC register.
IOUT2:
DAC Current Output 2. IOUT2 is a constant minus
IOUT1 , or IOUT1 + IOUT2 = constant (I full scale for
a fixed reference voltage).
Rfb: Feedback Resistor. The feedback resistor is pro-
Linearity Error
VREF:
VCC:
GND:
vided on the IC chip for use as the shunt feedback
resistor for the external op amp which is used to
provide an output voltage for the DAC. This on-
chip resistor should always be used (not an exter-
nal resistor) since it matches the resistors which
are used in the on-chip R-2R ladder and tracks
these resistors over temperature.
Reference Voltage Input. This input connects an
external precision voltage source to the internal
R-2R ladder. VREF can be selected over the range
of +10 to −10V. This is also the analog voltage in-
put for a 4-quadrant multiplying DAC application.
Digital Supply Voltage. This is the power supply
pin for the part. VCC can be from +5 to +15VDC.
Operation is optimum for +15VDC
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (VOS pin
10) will result in a linearity change of
For example, if VREF = 10V and pin 10 is 9mV offset from
IOUT1 and IOUT2 the linearity change will be 0.03%.
Pin 3 can be offset ±100mV with no linearity change, but the
logic input threshold will shift.
DS005608-23
a) End point test after
zero and fs adj.
DS005608-24
b) Best straight line
DS005608-25
c) Shifting fs adj. to pass
best straight line test
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 28 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting for
zero and full-scale. Linearity error is a parameter intrinsic to
the device and cannot be externally adjusted.
National’s linearity “end point test” (a) and the “best straight
line” test (b,c) used by other suppliers are illustrated above.
The “end point test’’ greatly simplifies the adjustment proce-
dure by eliminating the need for multiple iterations of check-
ing the linearity and then adjusting full scale until the linearity
is met. The “end point test’’ guarantees that linearity is met
after a single full scale adjust. (One adjustment vs. multiple
iterations of the adjustment.) The “end point test’’ uses a
standard zero and F.S. adjustment procedure and is a much
more stringent test for DAC linearity.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ±12LSB of the
final output value. Full-scale settling time requires a zero to
full-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC0830 series, full scale is VREF −1LSB.
For VREF = 10V and unipolar operation, VFULL-SCALE =
10,0000V–39mV 9.961V. Full-scale error is adjustable to
zero.
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DAC0832LCJ pdf, datenblatt
DAC0830 Series Application Hints (Continued)
FIGURE 6.
DS005608-37
FIGURE 7.
DS005608-38
2.3 Op Amp Considerations
The op amp used in Figure 7 should have offset voltage null-
ing capability (See Section 2.5).
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage applica-
tions. BI-FETop amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im-
portant in fast data throughput applications. The largest sta-
bility problem is the feedback pole created by the feedback
resistance, Rfb, and the output capacitance of the DAC. This
appears from the op amp output to the (−) input and includes
the stray capacitance at this node. Addition of a lead capaci-
tance, CC in Figure 8, greatly reduces overshoot and ringing
at the output for a step change in DAC output current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output volt-
age. Depending on the loading on the output of the amplifier
and the available op amp supply voltages (only ±12 volts in
many development systems), a reference voltage less than
10 volts may be necessary to obtain the full analog output
voltage range.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry can
be used to generate a bipolar output voltage from a fixed ref-
erence voltage. This, in effect, gives sign significance to the
MSB of the digital input word and allows two-quadrant multi-
plication of the reference voltage. The polarity of the refer-
ence can also be reversed to realize full 4-quadrant multipli-
cation: ±VREFx±Digital Code=±VOUT. This circuit is shown
in Figure 9.
This configuration features several improvements over exist-
ing circuits for bipolar outputs with other multiplying DACs.
Only the offset voltage of amplifier 1 has to be nulled to pre-
serve linearity of the DAC. The offset voltage error of the
second op amp (although a constant output voltage error)
has no effect on linearity. It should be nulled only if absolute
output accuracy is required. Finally, the values of the resis-
tors around the second amplifier do not have to match the in-
ternal DAC resistors, they need only to match and tempera-
ture track each other. A thin film 4-resistor network available
from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is
ideally suited for this application. These resistors are
matched to 0.1% and exhibit only 5 ppm/˚C resistance track-
ing temperature coefficient. Two of the four available 10 k
resistors can be paralleled to form R in Figure 9 and the
other two can be used independently as the resistances la-
beled 2R.
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the out-
put amplifier must always be nulled. Amplifier offset errors
create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0VDC as possible.
This is accomplished for the typical DAC — op amp connec-
tion (Figure 7) by shorting out Rfb, the amplifier feedback re-
sistor, and adjusting the VOS nulling potentiometer of the op
amp until the output reads zero volts. This is done, of course,
with an applied digital code of all zeros if IOUT1 is driving the
op amp (all one’s for IOUT2). The short around Rfb is then re-
moved and the converter is zero adjusted.
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