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DA28F016XS15 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer DA28F016XS15
Beschreibung 16-MBIT (1 MBIT x 16/ 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
DA28F016XS15 Datasheet, Funktion
E
28F016XS
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
SYNCHRONOUS FLASH MEMORY
n Effective Zero Wait-State Performance
up to 33 MHz
Synchronous Pipelined Reads
n SmartVoltage Technology
User-Selectable 3.3V or 5V VCC
User-Selectable 5V or 12V VPP
n 0.33 MB/sec Write Transfer Rate
n Configurable x8 or x16 Operation
n 56-Lead TSOP and SSOP Type I
Package
n Backwards-Compatible with 28F008SA
Command-Set
n 2 µA Typical Deep Power-Down
n 1 mA Typical Active ICC Current in
Static Mode
n 16 Separately-Erasable/Lockable
128-Kbyte Blocks
n 1 Million Erase Cycles per Block
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining very high read performance with the intrinsic
nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of
shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for
improved system performance. The innovative capabilities of the 28F016XS enable the design of direct-
execute code and mass storage data/file flash memory systems.
The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution
available today. Its synchronous pipelined read interface, flexible VCC and VPP voltages, extended cycling,
fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a
highly flexible memory component suitable for resident flash component arrays on the system board or
SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface
with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read
performance up to 33 MHz. The 28F016XS’s dual read voltage allows the same component to operate at
either 3.3V or 5.0V VCC. Programming voltage at 5V VPP minimizes external circuitry in minimal-chip, space
critical designs, while the 12.0V VPP option maximizes program/erase performance. Its high read performance
combined with flexible block locking enable both storage and execution of operating systems/application
software and fast access to large data tables. The 28F016XS is manufactured on Intel’s 0.6 µm ETOX IV
process technology.
November 1996
Order Number: 290532-004






DA28F016XS15 Datasheet, Funktion
28F016XS FLASH MEMORY
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DA28F016XS15 pdf, datenblatt
28F016XS FLASH MEMORY
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2.1 Lead Descriptions
Symbol
Type
Name and Function
A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is
in x8 mode. This address is latched in x8 data programs and ignored in x16
mode (i.e., the A0 input buffer is turned off when BYTE# is high).
A1 INPUT BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block.
A 128-Kbyte block is subdivided into an even and odd bank. A1 = 0 selects the
even bank and A1 = 1 selects the odd bank, in both byte-wide mode and word-
wide mode device configurations.
A2–A16
INPUT
WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block.
Address A1 and A7–16 select 1 of 2048 rows, and A2–6 select 16 of 512
columns. These addresses are latched during both data reads and programs.
A17–A20
INPUT BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These
addresses are latched during data programs, erase and lock-block operations.
DQ0–DQ7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, identifier or status data in the appropriate read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
CE0#, CE1#
RP#
OE#
INPUT/
OUTPUT
INPUT
INPUT
INPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program operations.
Outputs array or identifier data in the appropriate read mode; not used for
Status Register reads. Outputs floated when the chip is de-selected, the
outputs are disabled (OE# = VIH) or BYTE# is driven active.
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device is
de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE0# and
CE1# must be low to select the device.
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or
CE1# disables the device.
RESET/POWER-DOWN: RP# low places the device in a deep power-down
state. All circuits that consume static power, even those circuits enabled in
standby mode, are turned off. When returning from deep power-down, a
recovery time of tPHCH is required to allow these circuits to power-up.
When RP# goes low, the current WSM operation is terminated, and the device
is reset. All Status Registers return to ready, clearing all status flags. Exit from
deep power-down places the device in read array mode.
OUTPUT ENABLE: Drives device data through the output buffers when low.
The outputs float to tri-state off when OE# is high. CEx# overrides OE#, and
OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Data Register and Address
Latch. WE# is active low, and latches both address and data (command or
array) on its rising edge.
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