|
|
PDF D950-CORE Data sheet ( Hoja de datos )
| Número de pieza | D950-CORE | |
| Descripción | 16-Bit Fixed Point Digital Signal Processor DSP Core | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de D950-CORE (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
D950-CORE
16-Bit Fixed Point Digital Signal Processor (DSP) Core
PRELIMINARY DATA
s Performance
s 66 Mips - 15ns instruction cycle time
s Memory Organization
s HARVARD architecture
s Two 64k x 16-bit data memory spaces
s One 64k x 16-bit program memory space
s 2 stacks in data memory spaces
s Fast and Flexible Buses
s Two 16-bit address 16-bit data non-
multiplexed data buses
s One 16-bit address 16-bit data non-
multiplexed instruction bus
s Data Calculation Unit
s 16 x 16-bit parallel multiplier
s 40-bit barrel shifter unit
s 40-bit ALU
s Two 40-bit extended precision accumulators
s Fractional and integer arithmetic with support
for floating point and multi-precision
s 16-bit bit manipulation unit (BMU)
s Address Calculation Unit
s Two address calculation units with modulo
and bit-reverse capability
s 2 x 16-bit address registers
s 4 x 16-bit index registers
s 2 x 16-bit base and maximum address
registers for modulo addressing
s Program Control Unit
s 16-bit program counter
s 3 Hardware Loop Capabilities
s Power Consumption
s Single 3.3V power supply
s Low-power standby mode
s Electrical Characteristics
s Operating frequency down to DC
s Channels
s General purpose 8-bit I/O port
s Dedicated hardware for Emulation and Test,
IEEE 1149.1 (JTAG) interface compatible
DATA
CALCULATION
UNIT
ADDRESS
CALCULATION
UNIT
XA-bus
YA-bus
PROGRAM
CONTROL
UNIT
ID-bus
IA-bus
6
16
16
16
16
3
16
16
11 8
14
CONTROL PO/P7
TEST & EMULATION
s Peripherals and Memory
s Macrocells for peripherals such as the bus
switch unit, interrupt controller and DMA
controller
s Standard cells library, I/O library
s Memory generators for RAM and ROM
s Development Tools
s JTAG PC board with graphic windowed high
level source debugger for AS-DSP emulation
s Complete crash-barrier chain (assembler /
simulator / linker) running on PC and SUN,
s Complete GNU chain (assembler / simulator /
linker / C compiler / C debugger) for SUN
s VHDL model (SYNOPSYS & MENTOR)
4 September 1997
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice
1/89
1 page  
D950-Core
1 Introduction
The D950-Core is a general purpose programmable 16-bit fixed point Digital Signal Processor
Core, designed for multimedia, telecom and datacom applications. The D950-Core is a core
product, used in combination with standard or custom peripherals from the standard cell
library. The peripherals are implemented around the core on the same silicon die, for
application specific DSP silicon chip design.
The main blocks of the D950-Core include an arithmetic data calculation unit, a program
control unit and an address calculation unit, able to manage up to 64k (program) and 128k
(data) x 16-bit memory spaces. Standard peripherals from the macrocell library include an
Emulation Unit, a Bus Switch Unit, an Interrupt Controller, a DMA Controller, a Timer and a
Synchronous Serial Port. Memory can be added for programs or data and dedicated memory
cells can be generated by use of RAM and ROM memory generators. The development of
application specific peripherals is simplified by using the standard cells library.
A set of high level hardware and software development tools and a complete design package,
give the user a substantial advantages in the form of a performant design environment, rapid
prototyping, first time silicon success and built-in test strategies for a global solution in AS-DSP
development:
Figure 1.1 shows an architecture example for an AS-DSP used for audio decoding (Dolby
AC3, MPEG).
Figure 1.1 AS-DSP Architecture Example
CHANNEL 1
PERIPHERAL B
CHANNEL 0
PERIPHERAL A
CHANNEL 2
PERIPHERAL C
CHANNEL 3
PERIPHERAL D
IC
NO
TN
ET
RR
RO
UL
PL
TE
R
DMA CONTROLLER
D950-CORE
ON-CHIP MEMORY
X-BUS
ON-CHIP MEMORY
Y-BUS
ON-CHIP MEMORY
I-BUS
BUS
SWITCH
UNIT
TAP EMU
AS-DSP
DATA
MEMORY
PROGRAM
MEMORY
VR02015
5/89
2
5 Page 
D950-Core
3 FUNCTIONAL OVERVIEW
The D950-CORE is composed of three main units.
• Data Calculation Unit (DCU)
• Address Calculation Unit (ACU)
• Program Control Unit (PCU)
These units are organized in an HARVARD architecture around three bidirectional 16-bit
buses, two for data and one for instruction. Each of these buses is dedicated to an uni-
directional 16-bit address bus (XA/YA/IA).
An 8-bit general purpose parallel port (P0-P7) can be configured (input or output). A test
condition is attached to each bit to test external events. Each of these functional blocks are
discussed in detail in Section 4“BLOCK DESCRIPTION”.
Control of the chip is performed through interface pins related to interrupt, low-power mode,
reset and miscellaneous functions.
Clock input is provided on the CLKIN pin which is buffered to the output clocks.
Figure 3.1 Block Diagram
DATA
CALCULATION
UNIT
ADDRESS
CALCULATION
UNIT
XA-bus
YA-bus
6
16
16
16
16
PROGRAM
CONTROL
UNIT
ID-bus
IA-bus
3
16
16
11 8
CONTROL PO/P7
14
TEST & EMULATION
11/89
4
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet D950-CORE.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| D950-CORE | 16-Bit Fixed Point Digital Signal Processor DSP Core | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |