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DDC112UK Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer DDC112UK
Beschreibung Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 24 Seiten
DDC112UK Datasheet, Funktion
®
For most current data sheet and other product
information, visit www.burr-brown.com
DDC112
DDC112
Dual Current Input 20-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q MONOLITHIC CHARGE MEASUREMENT ADC
q DIGITAL FILTER NOISE REDUCTION:
3.2ppm, rms
q INTEGRAL LINEARITY:
±0.005% Reading ±0.5ppm FSR
q HIGH PRECISION, TRUE INTEGRATING
FUNCTION
q PROGRAMMABLE FULL SCALE
q SINGLE SUPPLY
q CASCADABLE OUTPUT
APPLICATIONS
q DIRECT PHOTOSENSOR DIGITIZATION
q CT SCANNER DAS
q INFRARED PYROMETER
q PRECISION PROCESS CONTROL
q LIQUID/GAS CHROMATOGRAPHY
q BLOOD ANALYSIS
Protected by US Patent #5841310
DESCRIPTION
The DDC112 is a dual input, wide dynamic range,
charge-digitizing analog-to-digital converter (ADC) with
20-bit resolution. Low level current output devices,
such as photosensors, can be directly connected to its
inputs. Charge integration is continuous as each input
uses two integrators; while one is being digitized, the
other is integrating.
For each of its two inputs, the DDC112 combines
current-to-voltage conversion, continuous integration,
programmable full-scale range, A/D conversion, and
digital filtering to achieve a precision, wide dynamic
range digital result. In addition to the internal program-
mable full-scale ranges, external integrating capacitors
allow an additional user-settable full-scale range of up
to 1000pC.
To provide single-supply operation, the internal ADC
utilizes a differential input, with the positive input tied
to VREF. When the integration capacitor is reset at the
beginning of each integration cycle, the capacitor
charges to VREF. This charge is removed in proportion
to the input current. At the end of the integration cycle,
the remaining voltage is compared to VREF.
The high-speed serial shift register which holds the
result of the last conversion can be configured to allow
multiple DDC112 units to be cascaded, minimizing
interconnections. The DDC112 is available in a SO-28
package and is offered in two performance grades.
CAP1A
CAP1A
IN1
CAP1B
CAP1B
CAP2A
CAP2A
IN2
CAP2B
CAP2B
AVDD AGND
CHANNEL 1
Dual
Switched
Integrator
CHANNEL 2
Dual
Switched
Integrator
VREF
DVDD DGND
∆Σ
Modulator
DCLK
Digital
Filter
Digital
Input/Output
DVALID
DXMIT
DOUT
DIN
Control
RANGE2
RANGE1
RANGE0
TEST CONV CLK
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-14121D
DDC112Printed in U.S.A. January, 2000
®






DDC112UK Datasheet, Funktion
THEORY OF OPERATION
The basic operation of the DDC112 is illustrated in Figure 1.
The device contains two identical input channels where each
performs the function of current-to-voltage integration fol-
lowed by a multiplexed analog-to-digital (A/D) conversion.
Each input has two integrators so that the current-to-voltage
integration can be continuous in time. The output of the four
integrators are switched to one delta-sigma converter via a
four input multiplexer. With the DDC112 in the continuous
integration mode, the output of the integrators from one side
of both of the inputs will be digitized while the other two
integrators are in the integration mode as illustrated in the
timing diagram in Figure 2. This integration and A/D con-
version process is controlled by the system clock, CLK.
With a 10MHz system clock, the integrator combined with
the delta-sigma converter accomplishes a single 20-bit con-
version in approximately 220µs. The results from side A and
side B of each signal input are stored in a serial output shift
register. The DVALID output goes LOW when the shift
register contains valid data.
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs, as shown in Figure 2. The integration and
conversion process is fundamentally independent of the data
retrieval process. Consequently, the CLK frequency and
DCLK frequencies need not be the same. DIN is only used
when multiple converters are cascaded and should be tied to
DGND otherwise. Depending on TINT, CLK, and DCLK, it
is possible to daisy chain over 100 converters. This greatly
simplifies the interconnection and routing of the digital
outputs in those cases where a large number of converters
are needed.
CAP1A
CAP1A
IN1
CAP1B
CAP1B
CAP2A
CAP2A
IN2
CAP2B
CAP2B
AVDD
AGND
Input 1
Dual
Switched
Integrator
Input 2
Dual
Switched
Integrator
FIGURE 1. DDC112 Block Diagram.
VREF
DVDD
DGND
∆Σ
Modulator
Digital
Filter
Digital
Input/Output
Control
DCLK
DVALID
DXMIT
DOUT
DIN
RANGE2
RANGE1
RANGE0
TEST CONV
CLK
IN1, Integrator A
IN1, Integrator B
IN2, Integrator A
IN2, Integrator B
Conversion in Progress
Integrate
Integrate
IN1B
IN2B
Integrate
Integrate
IN1A
IN2A
Integrate
Integrate
IN1B
IN2B
Integrate
Integrate
IN1A
IN2A
DVALID
FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode).
®
DDC112
6

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DDC112UK pdf, datenblatt
During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration.
Consequently, keeping track of the current status of CONV
is all that is needed to know the current state. Cont mode
operation corresponds to states 3-6. Two of the states, 3 and
6, only perform an integration (no m/r/az cycle).
mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra-
tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.
One interesting observation from the state diagram is that
the integrations always alternate between sides A and B.
This relationship holds for any CONV pattern and is inde-
pendent of the mode. States 2 and 7 insure this relationship
during the ncont mode.
When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the begin-
ning state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6 and 4-5. Inverting
CONV results in the states progressing through their sym-
metrical match.
TIMING EXAMPLES
Cont Mode
A few timing diagrams will now be discussed to help
illustrate the operation of the state machine. These are
shown in Figures 10 through 19. Table V gives generalized
timing specifications in units of CLK periods. Values in µs
for Table V can be easily found for a given CLK. For
example, if CLK = 10MHz, then a CLK period = 0.1µs. t6
in Table V would then be 479.4µs.
SYMBOL
t6
t7
DESCRIPTION
Cont mode m/r/az cycle
Cont mode data ready
t8 1st ncont mode data ready
t9 2nd ncont mode data ready
t10 Ncont mode m/r/az cycle
t11 Prepare side for integration
VALUE (CLK periods)
4794
4212
4212 ±3
4212 ±3
4548
9108
240
(tINT > 4794)
(tINT = 4794)
TABLE V. Timing Specifications Generalized in CLK Periods.
Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates
the current state in the state diagram. The following two
traces show when integrations and measurement cycles are
underway. The internal signal mbsy is shown next. Finally,
DVALID is given. As described in the data sheet, DVALID
goes active LOW when data is ready to be retrieved from the
DDC112. It stays LOW until DXMIT is taken LOW by the
user. In Figure 10 and the following timing diagrams, it is
assumed that DXMIT it taken LOW soon after DVALID
goes LOW. The text below the DVALID pulse indicates the
side of the data and arrows help match the data to the
corresponding integration. The signals shown in Figures 10
through 19 are drawn at approximately the same scale.
In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first
two states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either by side A or side B.
CONV
State 1
Integration
Status
m/r/az
Status
mbsy
2
3
Integrate A
4
Integrate B
m/r/az A
t6
5
Integrate A
m/r/az B
4
Integrate B
m/r/az A
DVALID
t=0
Power-Up
SYMBOL
t6
t7
DESCRIPTION
Cont mode m/r/az cycle
Cont mode data ready
t7
Side A
Data
VALUE (CLK = 10MHz)
479.4µs
421.2µs
421.2 ±0.3µs
(TINT > 479.4µs)
(TINT = 479.4µs)
FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).
®
DDC112
12
Side B
Data
Side A
Data
VALUE (CLK = 15MHz)
316.4µs
280.5µs
280.5 ±0.2µs
(TINT > 316.4µs)
(TINT = 316.4µs)

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