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DD28F032SA-070 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer DD28F032SA-070
Beschreibung 32-MBIT (2 MBIT X 16/ 4 MBIT X 8) FlashFile MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
DD28F032SA-070 Datasheet, Funktion
E
DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
n User-Selectable 3.3V or 5V VCC
n User-Configurable x8 or x16 Operation
n 70 ns Maximum Access Time
n 28.6 MB/sec Burst Write Transfer Rate
n 1 Million Typical Erase Cycles per Block
n 56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology
n 64 Independently Lockable Blocks
n Revolutionary Architecture
100% Backwards-Compatible with
Intel 28F016SA
Pipelined Command Execution
Program during Erase
n 2 mA Typical ICC in Static Mode
n 2 µA Typical Deep Power-Down
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly-advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/program solution for solid-
state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provide a highly flexible memory component suitable for high-density
memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA’s dual read voltage
enables the design of memory cards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.
December 1996
Order Number: 290490-005






DD28F032SA-070 Datasheet, Funktion
DD28F032SA
The DD28F032SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card information, ROM-
executable O/S or application code. Each block
has an associated nonvolatile lock-bit which
determines the lock status of the block. In
addition, the DD28F032SA has a master Write
Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits
are set.
The DD28F032SA contains three types of Status
Registers to accomplish various functions:
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory’s Status Register. This register, when
used alone, provides a straightforward upgrade
capability to the DD28F032SA from a
28F008SA-based design.
A Global Status Register (GSR) which informs
the system of Command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
64 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 4
and 5.
The DD28F032SA incorporates an open drain
RY/BY# output pin. This feature allows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array. Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the 16-Mbit Flash Product
Family User’s Manual.
The DD28F032SA also incorporates three chip-
enable input pins, CE0#, CE1# and CE2#. The
active low combination of CE0# and CE1# controls
the first 28F016SA. The active low combination of
CE0# and CE2# controls the second 28F016SA.
E
The BYTE# pin allows either x8 or x16
read/programs to the DD28F032SA. BYTE# at
logic low selects 8-bit mode with address A0
selecting between low byte and high byte. On the
other hand, BYTE# at logic high enables 16-bit
operation with address A1 becoming the lowest
order address and address A0 is not used (don’t
care). A device block diagram is shown in Figure
1.
The DD28F032SA is specified for a maximum
access time of 70 ns (tACC) at 5.0V operation
(4.75V to 5.25V) over the commercial temperature
range (0°C to +70°C). A corresponding maximum
access time of 150 ns at 3.3V (3.0V to 3.6V and
0°C to +70°C) is achieved for reduced power
consumption applications.
The DD28F032SA incorporates an Automatic
Power Saving (APS) feature which substantially
reduces the active current when the device is in
static mode of operation (addresses not
switching).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin is driven low. This mode provides additional
write protection by acting as a device reset pin
during power transitions. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
A CMOS standby mode of operation is enabled
when either CE0#, or both CE1# and CE2#,
transition high and RP# stays high with all input
control pins at CMOS levels.
2.0 DEVICE PINOUT
The DD28F032SA Standard 56-Lead Dual Die
TSOP Type I pinout configuration is shown in
Figure 2.
6

6 Page









DD28F032SA-070 pdf, datenblatt
DD28F032SA
E
4.1 Extended Status Registers Memory Map for Either 28F016SA No. 1 or
28F016SA No. 2
x8 MODE
RESERVED
GSR
RESERVED
BSR 31
RESERVED
RESERVED
.
.
.
A[20-0]
1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1F0000H
010002H
RESERVED
RESERVED
GSR
RESERVED
BSR 0
RESERVED
RESERVED
000006H
000005H
000004H
000003H
000002H
000001H
000000H
0490_04
Figure 4. Extended Status Register Memory
Map (Byte-Wide Mode)
x16 MODE
RESERVED
GSR
RESERVED
BSR 31
RESERVED
RESERVED
.
.
.
RESERVED
A[20-1]
F8003H
F8002H
F8001H
F8000H
08001H
RESERVED
GSR
RESERVED
BSR 0
RESERVED
RESERVED
00003H
00002H
00001H
00000H
0490_05
Figure 5. Extended Status Register Memory
Map (Word-Wide Mode)
12

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