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DAC8512EP Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer DAC8512EP
Beschreibung % V/ Serial Input Complete 12-Bit DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
DAC8512EP Datasheet, Funktion
a
FEATURES
Space Saving SO-8 or Mini-DIP Packages
Complete, Voltage Output with Internal Reference
1 mV/Bit with 4.095 V Full Scale
Single +5 Volt Operation
No External Components
3-Wire Serial Data Interface, 20 MHz Data Loading Rate
Low Power: 2.5 mW
APPLICATIONS
Portable Instrumentation
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals
+5 V, Serial Input
Complete 12-Bit DAC
DAC8512
FUNCTIONAL BLOCK DIAGRAM
CLR 6
LD 5
CS 2
CLK 3
SDI 4
REF
12-BIT DAC
12
DAC REGISTER
12
SERIAL REGISTER
1 VDD
8 VOUT
7 GND
GENERAL DESCRIPTION
The DAC8512 is a complete serial input, 12-bit, voltage output
digital-to-analog converter designed to operate from a single
+5 V supply. It contains the DAC, input shift register and
latches, reference and a rail-to-rail output amplifier. Built using
a CBCMOS process, these monolithic DACs offer the user low
cost, and ease of use in +5 V only systems.
Coding for the DAC8512 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to +4.095 V—for a one-millivolt-per-bit resolution.
It is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.
Serial interface is high speed, three-wire, DSP compatible with
data in (SDI), clock (CLK) and load strobe (LD). There is also
a chip-select pin for connecting multiple DACs.
A CLR input sets the output to zero scale at power on or upon
user demand.
The DAC8512 is specified over the extended industrial (–40°C
to +85°C) temperature range. DAC8512s are available in plas-
tic DIPs and SO-8 surface mount packages.
1.0
0.75
0.5
0.25
0
–0.25
–0.5
–0.75
–1.0
0
1024
2048
3072
DIGITAL INPUT CODE – Decimal
Linearity Error vs. Digital Input Code
4096
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996






DAC8512EP Datasheet, Funktion
DAC8512
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply.
P-CH
VDD
N-CH
VOUT
AGND
Figure 4. Equivalent Analog Output Circuit
Figure 4 shows an equivalent output schematic of the rail-to-rail
amplifier with its N channel pull down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P channel pull up device that can supply GND
terminated loads, especially at the low supply tolerance values of
4.75 volts. Figures 5 and 6 provide information on output swing
performance near ground and full-scale as a function of load. In
addition to resistive load driving capability the amplifier has also
been carefully designed and characterized for up to 500 pF ca-
pacitive load driving capability.
POWER SUPPLY
The very low power consumption of the DAC8512 is a direct
result of a circuit design optimizing use of the CBCMOS pro-
cess. By using the low power characteristics of the CMOS for
the logic, and the low noise, tight matching of the complemen-
tary bipolar transistors good analog accuracy is achieved.
For power consumption sensitive applications it is important to
note that the internal power consumption of the DAC8512 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CS, LD, and CLR pins. Since these inputs
are standard CMOS logic structures they contribute static
power dissipation dependent on the actual driving logic VOH and
VOL voltage levels. The graph in Figure 9 shows the effect on to-
tal DAC8512 supply current as a function of the actual value of
input logic voltage. Consequently use of CMOS logic vs. TTL
minimizes power dissipation in the static state. A VIL = 0 V on
the SDI, CS and CLR pins provides the lowest standby power
dissipation of 2.5 mW (500 µA × 5 V).
As with any analog system, it is recommended that the DAC8512
power supply be bypassed on the same PC card that contains the
chip. Figure 10 shows the power supply rejection versus frequen-
cy performance. This should be taken into account when using
higher frequency switched mode power supplies with ripple fre-
quencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
DAC8512 is the wide range of usable supply voltage. The part
is fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the DAC8512
is possible down to +4.3 volts. The minimum operating supply
voltage versus load current plot, in Figure 11, provides informa-
tion for operation below VDD = +4.75 V.
TIMING AND CONTROL
The DAC8512 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC out-
put voltage. After the new value is fully loaded in the serial in-
put register it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any
new data is loaded into the serial input register. At any time the
contents of the DAC register can be reset to zero by strobing
the CLR pin which causes the DAC output voltage to go to
zero volts. All of the timing requirements are detailed in Figure
1 along with the Table I Control-Logic Truth Table.
–6– REV. A

6 Page









DAC8512EP pdf, datenblatt
DAC8512
R1
100k
R2
5k+15V
7
17
0.1µF
6
18
12
AMP05
10
8
19
11
25
4 P1
100k
0.1µF
RCS
100
0mA IOUT 10mA
2.4µA/ BIT
OP295’s feedback loop. For the circuit values shown, the full-
scale output current is 1 mA which is given by the following
equation:
IOUT =
DW × 4.095V
R1
where DW = DAC8512’s binary digital input code.
+5V
0.1µF
VS
1
CS 2
CLR 6 DAC8512FP
LOAD
+5V
+15V
0.1µF
–15V
2
REF02 6
4
CS
CLR
LD
SCLK
SDI
0.1µF
1
2
6 DAC8512FZ
5
3
4
7
8
R3
3k
R4
1k
LD 5
83
SCLK
3
A1 1
2N2222
SDI 4
2
7
A1 = 1/2 OP295
R1
4.02k
P1
200
FULL-SCALE
ADJUST
Figure 32. A Single-Supply, Programmable Current
Source
The usable output voltage range of the current sink is +5 V to
+60 V. The low limit of the range is controlled by transistor
saturation, and the high limit is controlled by the collector-base
breakdown voltage of the 2N2222.
Figure 31. A High-Compliance, Digitally Controlled
Precision Current Source
A Single-Supply, Programmable Current Source
The circuit in Figure 32 shows how the DAC8512 can be used
with an OP295 single-supply, rail-to-rail output op amp to pro-
vide a digitally programmable current sink from VSOURCE that
consumes less than 3.8 mA, maximum. The DAC’s output volt-
age is applied across R1 by placing the 2N2222 transistor in the
A Digitally Programmable Window Detector
A digitally programmable, upper/lower limit detector using two
DAC8512s is shown in Figure 33. The required upper and
lower limits for the test are loaded into each DAC individually
by controlling HDAC/LDAC. If a signal at the test input is not
within the programmed limits, the output will indicate a logic
zero which will turn the red LED on.
+5V
+5V
1k
0.1µF
1
6
2 DAC8512
5
38
VIN
+5V
+5V
0.1µF
R1
604
+5V
R2
604
2
1/6
74HC05
1
CLR
HDAC/LDAC
LD
SCLK
SDI
4
7
+5V
0.1µF
1
6
2 DAC8512
5
38
4
7
3
5
C1
4
2
7
C2
6
12
1
C1, C2 = 1/4 CMP-404
RED LED
T1
PASS/FAIL
GREEN LED
T1
34
1/6
74HC05
Figure 33. A Digitally Programmable Window Detector
–12–
REV. A

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