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DAC8043GP Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer DAC8043GP
Beschreibung 12-Bit Serial Input Multiplying CMOS D/A Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
DAC8043GP Datasheet, Funktion
a
FEATURES
12-Bit Accuracy in an 8-Pin Mini-DIP
Fast Serial Data Input
Double Data Buffers
Low ؎1/2 LSB Max INL and DNL
Max Gain Error: ؎1 LSB
Low 5 ppm/؇C Max Tempco
ESD Resistant
Low Cost
Available in Die Form
APPLICATIONS
Autocalibration Systems
Process Control and Industrial Automation
Programmable Amplifiers and Attenuators
Digitally-Controlled Filters
12-Bit Serial Input
Multiplying CMOS D/A Converter
DAC8043
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying
DAC in a space-saving 8-pin mini-DIP package. Featuring serial
data input, double buffering, and excellent analog performance,
the DAC8043 is ideal for applications where PC board space is
at a premium. Also, improved linearity and gain error performance
permit reduced parts count through the elimination of trimming
components. Separate input clock and load DAC control lines
allow full user control of data loading and analog output.
The circuit consists of a 12-bit serial-in, parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC, and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the LD input
pin. Data in the DAC register is converted to an output current
by the D/A converter.
The DAC8043’s fast interface timing may reduce timing design
considerations while minimizing microprocessor wait states. For
applications requiring an asynchronous CLEAR function or more
versatile microprocessor interface logic, refer to the PM-7543.
Operating from a single +5 V power supply, the DAC8043 is
the ideal low power, small size, high performance solution to
many application problems. It is available in plastic and cerdip
packages that are compatible with auto-insertion equipment.
PIN CONNECTIONS
8-Pin Epoxy DIP
(P-Suffix)
8-Pin Cerdip
(Z-Suffix)
16-Lead Wide-Body SOL
(S-Suffix)
N.C. 1
16 N.C.
N.C. 2
15 N.C.
VREF 3
14 VDD
RFB 4 DAC8043 13 CLK
IOUT
5
TOP VIEW
(Not to Scale)
12
SRI
GND 6
11 LD
GND 7
10 N.C.
N.C. 8
9 N.C.
NC = NO CONNECT
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






DAC8043GP Datasheet, Funktion
DAC8043
PARAMETER DEFINITIONS
INTEGRAL NONLINEARITY (INL)
This is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to PMI 1988 Data Book section 11 for additional digital-
to-analog converter definitions.
INTERFACE LOGIC INFORMATION
The DAC8043 has been designed for ease of operation. The
timing diagram illustrates the input register loading sequence.
Note that the most significant bit (MSB) is loaded first.
Once the input register is full, the data is transferred to the
DAC register by taking LD momentarily low.
DIGITAL SECTION
The DAC8043’s digital inputs, SRI, LD, and CLK, are TTL
compatible. The input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located under the
typical performance characteristics curves. Maintaining the digi-
tal input voltage levels as close as possible to the supplies, VDD
and GND, minimizes supply current consumption.
The DAC8043’s digital inputs have been designed with ESD re-
sistance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 1 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the in-
puts are shunted to the supply and ground rails through forward
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
GENERAL CIRCUIT INFORMATION
The DAC8043 is a 12-bit multiplying D/A converter with a very
low temperature coefficient. It contains an R-2R resistor ladder
network, data input and control logic, and two data registers.
Figure 1. Digital Input Protection
The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.
A simplified circuit of the DAC8043 is shown in Figure 2. An
inverted R-2R ladder network consisting of silicon-chrome,
highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs
of NMOS current-steering switches.
These switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regard-
less of digital input code. This constant current results in a con-
stant input resistance at VREF equal to R. The VREF input may
be driven by any reference voltage or current, ac or dc that is
within the limits stated in the Absolute Maximum Ratings.
The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor, they can introduce bit errors if all
are of the same RON resistance value. They were designed such
that the switch “ON” resistance be binarily scaled so that the
voltage drop across each switch remains constant. If, for ex-
ample, switch 1 of Figure 2 was designed with an “ON” resis-
tance of 10 , switch 2 for 20 , etc., a constant 5 mV drop will
then be maintained across each switch.
Write Cycle Timing Diagram
–6–
REV. C

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