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DAC7724NB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer DAC7724NB
Beschreibung 12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 15 Seiten
DAC7724NB Datasheet, Funktion
®
DAC7724
DAC7725
DAC7724
DAC7725
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q LOW POWER: 250mW max
q SINGLE SUPPLY OUTPUT RANGE: +10V
q DUAL SUPPLY OUTPUT RANGE: ±10V
q SETTLING TIME: 10µs to 0.012%
q 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
q RESET TO MID-SCALE (DAC7724) OR
ZERO-SCALE (DAC7725)
q DATA READBACK
q DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
q PROCESS CONTROL
q CLOSED-LOOP SERVO-CONTROL
q MOTOR CONTROL
q DATA ACQUISITION SYSTEMS
GND
DB0-DB11
12 I/O
Buffer
Input
Register A
DESCRIPTION
The DAC7724 and DAC7725 are 12-bit quad voltage
output digital-to-analog converters with guaranteed
12-bit monotonic performance over the specified tem-
perature range. They accept 12-bit parallel input data,
have double-buffered DAC input logic (allowing simul-
taneous update of all DACs), and provide a readback
mode of the internal input registers. An asynchronous
reset clears all registers to a mid-scale code of 800H
(DAC7724) or to a zero-scale of 000H (DAC7725). The
DAC7724 and DAC7725 can operate from a single
+15V supply, or from +15V and –15V supplies.
Low power and small size per DAC make the DAC7724
and DAC7725 ideal for automatic test equipment,
DAC-per-pin programmers, data acquisition systems,
and closed-loop servo-control. The DAC7724 and
DAC7725 are available in a PLCC-28 or a SO-28
package, and offer guaranteed specifications over the
–40°C to +85°C temperature range.
VDD
VCC VREFH
DAC
Register A
DAC A
VOUTA
Input
Register B
DAC
Register B
DAC B
A0
A1
R/W
CS
Control
Logic
Input
Register C
DAC
Register C
DAC C
Input
Register D
DAC
Register D
DAC D
VOUTB
VOUTC
VOUTD
RESET LDAC VREFL
VSS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1517B
Printed in U.S.A. April, 2000






DAC7724NB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
200H
400H
600H 800H A00H C00H
Digital Input Code
E00H FFFH
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
200H
400H 600H 800H A00H C00H
Digital Input Code
E00H FFFH
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
200H
400H 600H 800H A00H C00H
Digital Input Code
E00H FFFH
ZERO-SCALE ERROR vs TEMPERATURE
(Code 004H)
2.0
1.5
1.0
DAC B
DAC A
DAC D
0.5
0
–0.5
DAC C
–1.0
–1.5
–2.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
2.0
1.5
1.0
DAC A
0.5
DAC B
DAC D
0
–0.5
DAC C
–1.0
–1.5
–2.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
000H
200H
CURRENT vs CODE
All DACs Sent to Indicated Code
VREFH
VREFL
400H 600H 800H A00H C00H
Digital Input Code
E00H FFFH
®
DAC7724, 7725
6

6 Page









DAC7724NB pdf, datenblatt
THEORY OF OPERATION
The DAC7724 and DAC7725 are quad voltage output,
12-bit digital-to-analog converters (DACs). The architecture
is a classic R-2R ladder configuration followed by an opera-
tional amplifier that serves as a buffer, as shown in Figure 1.
Each DAC has its own R-2R ladder network and output op-
amp, but all share the reference voltage inputs. The mini-
mum voltage output (“zero-scale”) and maximum voltage
output (“full-scale”) are set by the external voltage refer-
ences (VREFL and VREFH, respectively). The digital input is
a 12-bit parallel word and the DAC input registers offer a
readback capability. The converters can be powered from a
single +15V supply or a dual ±15V supply. Each device
offers a reset function which immediately sets all DAC
registers and DAC output voltages to mid-scale (DAC7724,
code 800H) or to zero-scale (DAC7725, code 000H). See
Figures 2 and 3 for the basic operation of the DAC7724/25.
RF
R RR RRRR
2R 2R
2R 2R 2R 2R 2R 2R 2R
VOUT
FIGURE 1. DAC7724/25 Architecture.
VREFH
VREFL
+10.00V
0.1µF
0V to +10V
0V to +10V
Reset DACs(1)
Load DAC Registers
Data Bus
DAC7724
DAC7725
1 VREFH
2 VOUTB
3 VOUTA
4 VSS
5 GND
6 RESET
7 LDAC
8 DB0
9 DB1
10 DB2
11 DB3
12 DB4
13 DB5
14 DB6
VREFL
VOUTC
VOUTD
VCC
VDD
CS
28
27
26
25
24
23
A0 22
A1 21
R/W 20
DB11 19
DB10 18
DB9 17
DB8 16
DB7 15
0V to +10V
0V to +10V
Chip Select
Address Bus
or Decoder
Read/Write
Data Bus
+15V
+
0.1µF
1µF to 10µF
+5V
+
0.1µF
1µF to 10µF
NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7724 and to code 000H on the DAC7725.
FIGURE 2. Basic Single-Supply Operation of the DAC7724/25.
®
DAC7724, 7725
12

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