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PDF AN5394FB Data sheet ( Hoja de datos )
| Número de pieza | AN5394FB | |
| Descripción | RGB processor IC for the HDTV(Japan) and wide-screen TV | |
| Fabricantes | Panasonic Semiconductor | |
| Logotipo |  |
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ICs for TV
AN5392FBQ
Luminance and color difference drive/cutoff signal processor IC
with I2C bus
s Overview
The AN5392FBQ is an RGB processor IC which
converts the luminance and color difference signal into a
primary color signal. This IC supports all kinds of input
signal from hi-vision, wide, NTSC, PAL, VGA, etc. for
maximum rationalization and high performance of the
end products.
48
49
16.2±0.3
14.0±0.2
Unit: mm
33
32
s Features
• A wider band signal processing (Y: 30 MHz/−3 dB,
color difference: 15 MHz/−3 dB)
• High picture quality thanks to a large variety of built-in
correction circuit for Y signal
• Y, C−Y signal conversion circuit built in for RGB signal
for a personal computer
• Possible to mount in a high density thanks to SMD pack-
age
64
1
(1.0)
0.8
17
16
+0.10
0.35–0.05
Seating plane
QFS064-P-1414
0.55±0.2
s Applications
• Hi-vision TV, wide TV, projection TV, plasma display
panel (PDP)
1
1 page  
ICs for TV
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
Parameter
Symbol
Conditions
Min Typ Max Unit
Y-system (continued)
DC regeneration ratio 1
DC1 Input signal: APL 10% → 90%,
APL det. pin 0 V
96 102 107 %
DC regeneration ratio 2
DC regeneration ratio 3
Output blooming level
DC2 Input signal: APL 10% → 90%,
65 75 85
DC regeneration SW/on, polarity: −
DC3 Input signal: APL 10% → 90%,
115 125 135
DC regeneration SW: On, polarity: +
VBL Blooming DC = 3.8 V,
pin 43: 0 V, brightness: max.
5.7 6.7 7.7
%
%
V
Output blooming level
variation amount
White gradation correction 1 *2
∆VBL
Yγ1
White gradation correction 2 *2 Yγ2
Blooming DC = 3.8 V → 4.2 V,
pin 43: 0 V, brightness: max.
Gain: max., level: typ. → max.
White gradation SW: On
Gain: max., level: typ. → min.
White gradation SW: On
−1.18 − 0.93 − 0.68 V
9.0 14 18.0 %
−24 −18 −12 %
Black extension
characteristics 1 *3
YBL1 Output amplitude: 0 V[p-p]
Level: typ., gain: min. → max.
− 0.1 0 +0.1 V
Black extension
characteristics 2 *3
YBL2 Output amplitude: 1.0 V[0-p]
Level: typ., gain: min. → max.
− 0.49 − 0.37 − 0.25 V
Black extension
characteristics 3 *3
Black extension
characteristics 4 *4
YBL3
YBL4
Output amplitude: 2.2 V[0-p]
Level: typ., gain: min. → max.
Black detection: Open → 3 V
Level: typ., gain: typ.
− 0.1 0 +0.1 V
−1.10 − 0.82 − 0.55 V
Black extension
characteristics 5 *4
YBL5 Black detection: Open → 3 V
Level: typ., gain: max.
−2.00 −1.55 −1.00 V
Black extension
characteristics 6 *4
White character correction 1 *2
YBL6
VW1
White character correction 2 *2 VW2
White character correction off *2 WOFF
ABL off *5
VABL1
ABL start 1*5
VABL2
Black detection: Open → 3 V
Level: min. → max., gain: typ.
Blooming DC adjustment
Level: max., gain: min. → typ.
Blooming DC adjustment
Level: min., gain: min. → max.
PR, PB input: +0.2 V[p-p]
Level: max., gain: min. → max.
ABL/ACL pin: 7.5 V
Level: min., gain: min. → max.
ABL/ACL pin: 3 V
Level: min. → max., gain: max.
− 0.48 − 0.30 − 0.12 V
10.0 25.0 40.0 %
−9.3 0 9.3 %
− 0.2 0 +0.2 V
− 0.1 0 +0.1 V
0.28 0.39 0.50 V
Note) *2: Control a blooming DC voltage (pin 46)
*3: Black gradation SW: On
*4: Black gradation SW: On, brightness: max.
*5: ABL SW: On, brightness: max.
5
5 Page 
ICs for TV
AN5392FBQ
s Electrical Characteristics at VCC1 = 9 V, VCC2 = 5 V, Ta = 25°C (continued)
• Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min Typ Max Unit
OSD (continued)
OSD input dynamic range
DOSD
OSD output amplitude
OSD
ambient temperature dependency ∆T
−20°C to +70°C
1.4 V[p-p]
±2
%
Cutoff drive
Drive variable range (G)
Blanking delay
Pedestal fluctuation
to contrast variation
∆GD
tdBLK1
∆VPCONT
Drive G: min. → max.
BLK → BLK output
Contrast: min. → max.
2.6
40
0
dB
ns
mV
Pedestal fluctuation
to color variation
∆VPCOLOR Contrast: min. → max.
0 mV
Pedestal fluctuation
to tint variation
∆VPTINT
0 mV
Output pedestal potential
∆VP
ambient temperature dependency ∆T
−20°C to +70°C
−1.2 mV/°C
Spot killer operation
I2C DAC
VSP Lower 9 V-system VCC, pin 33: C = 10 µF 7.8
V
4 · 5 · 6 DAC DNLE
L1 1LSB = {data (max.) − data (min.)}/ 0.1 1.0 1.9 LSB
(2N−1)
Step
8-bit DAC DNLE
(excluding 40, 80, C0)
L2 1LSB = {data (max.) − data (min.)}/ 0.1 1.0 1.9 LSB
(2N−1)
Step
8-bit DAC DNLE
(only for 40, 80, C0)
L3 1LSB = {data (max.) − data (min.)}/ −1.0 1.0 +2.0 LSB
(2N−1)
Step
7-bit DAC DNLE
(excluding 40)
L4 1LSB = {data (max.) − data (min.)}/ 0.1 1.0 1.9 LSB
(2N−1)
Step
7-bit DAC DNLE
(only for 40)
L5 1LSB = {data (max.) − data (min.)}/ −1.0 1.0 +2.0 LSB
(2N−1)
Step
Y, U, V
Y, U, V signal delay
Y, U, V input dynamic range
Y, U, V matrix ratio 4
tdYUV R, G, B in → Y, C−Y out, f = 5 MHz 5 ns
DYUV
1.4
V
MYUV4 R-in: Sine wave 0.2 V[p-p],
f = 1 MHz → R-Y out
0.7 Times
Y, U, V matrix ratio 5
MYUV5 R-in: Sine wave 0.2 V[p-p],
f = 1 MHz → B-Y out
− 0.3 Times
Y, U, V matrix ratio 6
MYUV6 G-in: Sine wave 0.2 V[p-p],
f = 1 MHz → R-Y out
− 0.59 Times
Y, U, V matrix ratio 7
MYUV7 G-in: Sine wave 0.2 V[p-p],
f = 1 MHz → B-Y out
− 0.59 Times
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AN5394FB.PDF ] | |
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