|
|
PDF AN5385K Data sheet ( Hoja de datos )
| Número de pieza | AN5385K | |
| Descripción | Contour correction IC | |
| Fabricantes | Panasonic Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AN5385K (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
Serial EEPROM Endurance
AN537
Everything a System Engineer Needs to Know About Serial EEPROM Endurance
The term “endurance” has become a confusing param-
eter for both users and manufacturers of EEPROM
products. This is largely because many semiconductor
vendors treat this important application-dependent reli-
ability parameter as a vague specmanship topic. As a
result, the system engineer often designs without proper
reliability information or under-utilizes the EEPROM as
an effective solution.
Endurance (the number of times an EEPROM cell can be
erased and rewritten without corrupting data) is a mea-
sure of the device’s reliability, not its parametric perfor-
mance. As such, endurance is not achieved by some-
how making EEPROM devices more durable or robust to
extend the life of the intrinsic erase/write cycle, but rather
by reducing their defect-density failure rates. This has a
direct impact on the design engineer characterizing
EEPROM memory needs for an application and evaluat-
ing components from various manufacturers. The sys-
tem design engineer needs to understand not only the
relationship between the application, expected use and
failure mechanisms, but also how the manufacturer has
arrived at published endurance data for its components.
This tutorial volume is intended to clarify some of the
issues in the industry and provide a tool for the system
design engineer, the system reliability engineer, and the
component engineer to determine EEPROM reliability
and understanding how to apply it to actual application
requirements. It will examine four main areas:
• CMOS floating gate memory cell operation and char-
acteristics
• Significant process and design interactions and en-
durance characterization variables
• Common misinterpretations of endurance
• Determining some real world application reliability
requirements
EEPROM MEMORY CELL
OPERATION AND
CHARACTERISTICS
In discussing endurance characteristics of EEPROMs,
it’s important to review how these components operate,
and why and how they fail. Figure 1 illustrates a CMOS
floating gate EEPROM cell, including voltage conditions
for READ, ERASE, and WRITE operations. To erase or
write, the row select transistor must have the relatively
high potential of 20V. This voltage is internally gener-
ated on chip by a charge pump, with the only external
voltage required being VDD. The only difference be-
tween an ERASE and a WRITE is the direction of the
applied field potential relative to the polysilicon floating
gate.
When 20V is applied to the polysilicon memory cell gate
and 0V is applied to the bit line drain (column), electrons
tunnel from the substrate through the 90-angstrom Tun-
nel Dielectric (TD) oxide to the polysilicon floating gate
until the polysilicon floating gate is saturated with charge.
The cell is now at an ERASE state of “1”. When 0V is
applied to the polysilicon memory cell gate and 20V is
applied to the bit line drain (column), electrons tunnel
from the polysilicon floating gate through the TD oxide to
the substrate. The cell then is at a WRITE state of “0”.
This sequence of the transfer of charge onto the floating
gate (ERASE) and the electrical removal of that charge
from the floating gate (WRITE) is one ERASE/ WRITE
cycle, or “E/W cycle.”
The field (applied voltage to an oxide thickness) across
the tunneling path created by the 20V potential is ex-
tremely high in order to transfer the electrons. Over the
cell’s “application time,” as measured by E/W cycles, the
EEPROM cell begins to wear out due to the field stress.
The EEPROM cell wears out as the number of cycles
increase resulting in the voltage margin between the
ERASE and WRITE states decreasing until finally there
is not enough margin for the EEPROM sense amp to
detect a difference in the two states during a READ.
Failure is defined as when the sense amp can no longer
reliably differentiate logic state changes.
Figure 2 (single cell EEPROM endurance characteris-
tics) illustrates that the intrinsic wear out point for a
normal cell with specified dimensions and electrical
characteristics is very acceptable, in excess of 2 million
E/W cycles. Failures at lower cycles are due mostly to
very small defects or imperfections in the oxide or
silicon-to-oxide interface.
8
© 1992 Microchip Technology Inc.
8-15
DS00537A-page 1
1 page  
Serial EEPROM Endurance
number of E/W cycles per day require only a small
number of bits. Last number redial in a telephone, for
example, consumes many E/W cycles per day, but
utilizes only a few bytes for this function. By contrast,
speed dial storage in that same telephone consumes
only a fraction of E/W cycles per day, but requires a
relatively large segment of bits to accommodate the
many speed dial options. In such an application, the
same serial EEPROM normally performs both functions
at different address locations.
ENDURANCE DATA FROM THE
CUSTOMER’S PERSPECTIVE
Unfortunately, an industry standard for an endurance
test method has yet to be adopted. Since endurance
data is not baselined, the process of evaluating endur-
ance becomes that much more complicated for the
system designer and reliability engineer.
It is not uncommon for customers to request endurance
data from many semiconductor vendors. All vendors
would be expected to comment that they experience a
low failure rate through 100K E/W cycles. While this can
be a true statement, it can also be a very incomplete
statement. It is extremely doubtful that all vendors test
their components to the same conditions. Yet the
variables within endurance testing are extremely signifi-
cant. Small differences in text protocol can have enor-
mous differences. Pattern, cycling mode, temperature
and array size, for example, are the most significant
testing variables.
First, memory cell failure rates are defect density driven
up to the intrinsic wear out point. Existing defects in a
cell, while not causing failure initially, are stressed
during every transfer of electrons through the TD oxide
until they eventually cause cell failure. Worst case
testing would be to erase and write each bit, which is
what a write all “0”s pattern with an auto-erase of “1”
routine will perform. Indeed, this write all “0”s test
pattern will produce very different results than a check-
erboard test pattern of alternating “1”s and “0”s within a
byte, since cells are changed more often writing all “0”s
than in an alternating “1” and “0” write pattern. The
resultant failure rate differences are indicated on the
pattern effect graph in Figure 4.
In actual use, however, a system will experience a
random pattern much more like the alternating “1”s and
“0”s pattern than the more stressful all “0”s pattern. The
key point for system designers is to determine how
accurate a test routine has been used to determine a
particular manufacturer’s endurance data, and make
the appropriate judgement on that part’s expected en-
durance in the application.
FIGURE 4 - PATTERN EFFECT ON ENDURANCE TESTING
Cumulative
Failure Rate
Byte Write 0
Pattern
Alternating "1"
and "0" Pattern
8
© 1992 Microchip Technology Inc.
Erase/Write Cycles
8-19
DS00537A-page 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AN5385K.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AN5385K | Contour correction IC | Panasonic Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |