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PDF AN983 Data sheet ( Hoja de datos )
| Número de pieza | AN983 | |
| Descripción | PCI/miniPCI-to-Ethernet LAN Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AN983 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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AN983B/AN983BL
PCI/miniPCI-to-Ethernet LAN
Controller
DATASHEET
Rev. 1.8
MAY. 2003
DataSheet4U.com
DataShee
ADMtek.com.tw
Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications
and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features
or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility
whatsoever for conflicts or incompatibilities arising from future changes to them.
The products may contain design defects or errors known as errata, which may cause the product to deviate from published
specifications. Current characterized errata are available on request. To obtain latest documents, please contact your local
ADMtek sales office or your distributor or visit ADMtek’s website at http://www.ADMtek.com.tw
*Third-party brands and names are the property of their respective owners.
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AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
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CSR26 (offset = a8h) - PAR1, physical address register 1............................... 44
CSR27 (offset = ach) - MAR0, multicast address register 0 ............................ 45
CSR28 (offset = b0h) - MAR1, multicast address register 1............................ 45
Operation Mode Register (Memory base offset 0FCh) .................................... 46
7.3. PHY Registers (ACCESSED by csr9 MDI/MMC/MDO/MDC) ......................... 47
7.3.1. Transceiver registers Descriptions .......................................................... 47
7.4. Descriptors and Buffer Management................................................................. 51
7.4.1 Receive descriptor.................................................................................... 52
7.4.1.1 Receive Descriptor Table.............................................................. 52
7.4.1.2 Receive Descriptor Descriptions................................................... 52
RDES0 .............................................................................................................. 52
RDES1 .............................................................................................................. 53
RDES2 .............................................................................................................. 53
RDES3 .............................................................................................................. 53
7.4.2. Transmit Descriptor ................................................................................ 53
7.4.2.1. Transmit Descriptor Table ........................................................... 53
7.4.2.2. Transmit Descriptor Descriptions ................................................ 54
TDES0...............................D..a..t.a..S..h..e..e..t.4..U....c..o..m....................................................... 54
TDES1............................................................................................................... 54
TDES2............................................................................................................... 55
TDES3............................................................................................................... 55
8. FUNCTIONAL DESCRIPTIONS............................................................................. 56
8.1 Initialization Flow............................................................................................... 56
8.2 Network Packet Buffer Management .................................................................. 57
8.2.1 Descriptor Structure Types ...................................................................... 57
8.2.2 The point of descriptor management ....................................................... 59
8.3 Transmit Scheme and Transmit Early Interrupt ................................................. 61
8.3.1 Transmit flow........................................................................................... 61
8.3.2 Transmit pre-fetch data flow.................................................................... 61
8.3.3 Transmit early interrupt Scheme.............................................................. 62
8.4 Receive scheme and Receive early interrupt scheme.......................................... 63
8.5 Network Operation.............................................................................................. 65
8.5.1 MAC Operation ....................................................................................... 65
8.5.2 Transceiver Operation.............................................................................. 66
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Rev. 1.8
ADMtek Inc.
www.admtek.com.tw
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AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
3. FEATURES
INDUSTRY STANDARD
IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
PCI Specification 2.2 compliant
ACPI and PCI power management Ver.1.1 compliant
Support PC99 wake on LAN
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FIFO
Provides two independent long FIFOs with 2k bytes each for transmission and receiving
Pre-fetch up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
Retransmits collided packet without reload from host memory within 64 bytes.
Automatically retransmits FIFO under-run packet with maximum drain threshold until 3
times retry failure and that will not influence the registers and transmit threshold of next
packet
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PCI I/F
Provides 32-bit PCI bus master data transfer
Supports PCI clock with frequency from 0Hz to 33MHz
Supports network operation with PCI system clock from 20MHz to 33MHz
Provides performance meter, PCI bus master latency timer, for tuning the threshold to
enhance the performance
Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce
host CPU utilization
Supports memory-read, memory-read-line, memory-read-multiple, memory-write,
memory-write-and-invalidate command while being bus master
Supports big or little endian byte ordering
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EEPROM/BOOT ROM I/F
Provides write-able Flash ROM and EPROM as boot ROM with size up to 128kB
Provides PCI to access boot ROM by byte, word, or double word
Re-writes Flash boot ROM through I/O port by programming register
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Rev. 1.8
ADMtek Inc.
www.admtek.com.tw
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet AN983.PDF ] | |
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