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PDF CXP973F064 Data sheet ( Hoja de datos )
| Número de pieza | CXP973F064 | |
| Descripción | CMOS 16-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP973F064
CMOS 16-bit Single Chip Microcomputer
Description
The CXP973F064 is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, I2C bus interface, timer, PWM output
circuit, programmable pattern generator, remote
control receive circuit, parallel interface, FLASH
ROM interface, and as well as basic configurations
like a 16-bit CPU, ROM, RAM, and I/O port.
This LSI also provides the sleep/stop functions that
enable lower power consumption.
100 pin QFP (Plastic) 100 pin LQFP (Plastic)
Features
104 pin LFLGA (Plastic)
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-
purpose register of 16-bit × 8-pin × 16-bank
configuration
• Minimum instruction cycle
58.8ns at 34MHz operation (3.0 to 3.6V)
66.7ns at 30MHz operation (2.7 to 3.6V)
• Incorporated EEPROM capacity 256K bytes
• Incorporated RAM capacity
11.5K bytes
• Peripheral functions
— A/D converter
8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55µs at 40MHz)
— Serial interface
Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels
— I2C bus interface
64-byte buffer RAM
(supports master/slave and automatic transfer mode)
— Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels, watchdog timer
— PWM output circuit
14-bit PWM, 4 channels
(2-channel of binary output switch function by PPG)
— Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel
— Remote control receive circuit 8-bit pulse measurement counter, 10-stage FIFO
— Parallel interface
External register interface (8-bit parallel bus), 4-chip select
• Interruption
• Standby mode
• Package
• Piggy/evaluation chip
• Mask ROM
33 factors, 33 vectors, multi-interruption and priority selection possible
Sleep/stop
100-pin plastic QFP
100-pin plastic LQFP
104-pin plastic LFLGA
CXP971000
CXP972032/973032/973064
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99Z25B15-PS
1 page  
Pin Assignment 3 (Top View) 104-pin LFLGA package
CXP973F064
1 2 3 4 5 6 7 8 9 10 11 12 13
A 97 95 92 90 87 84 82 80 77
PB0 PA6 PA3 PA1 VDD PH6 PH4 PH2 PK6
B 99 96 93 91 88 85 81 76 75
PB2 PA7 PA4 PA2 VSS PH7 PH3 PK5 PK4
C 2 100
98 94 89 86 83 79 78
74 72
PB5 PB3
PB1 PA5 PA0 PWE PH5 PH1 PH0
PK3 PK1
D5 1 3
73 70 69
PC0 PB4 PB6
PK2 AVDD AVREF
E7 6 4
71 68 67
PC2 PC1 PB7
PK0 AVSS PJ7
F 10 9 8
66 65 64
PC5 PC4 PC3
PJ6 PJ5 PJ4
G 12 13 11
63 61 62
PC7 VSS PC6
PJ3 PJ1 PJ2
H 15 16 14
58 60 59
PD1 PD2 PD0
PI6 PJ0 PI7
J 17 18 19
54 56 57
PD3 PD4 PD5
K 20 21 23
PI3 PI4 PI5
53 51 55
PD6 PD7 PE1
PI2 PI0 VSS
L 22 24
28 30 33 36 41 46 48
50 52
PE0 PE2
PE6 PF0 PF3 PF6 EXTAL PG3 PG5
PG7 PI1
M 25 26 32 35 38 40 43 45 49
PE3 PE4 PF2 PF5 RST XTAL PG0 PG2 PG6
N 27 29 31 34 37 39 42 44 47
PE5 PE7 PF1 PF4 PF7 VSS VDD PG1 PG4
Note) 1. PWE (Pin C7) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins B7, E12, G2, K13 and N8) must be connected to GND.
3. VDD and AVDD (Pins A7, D12 and N9) must be connected to VDD.
–5–
5 Page 
CXP973F064
Pin
PF6/T1
PF7/T2
Circuit format
T1
PF register
("1" after a reset)
PFSL register
("0" after a reset)
Internal data bus
RD
1
MPX
0
After a reset
"H" level
T2
PF register
("1" after a reset)
PFSL register
("0" after a reset)
Internal data bus
1
MPX
0
RD
PF register write
Reset
SQ
R
∗
"H" level
("H" level at ON
resistance of
pull-up transistor
by a reset.)
∗ Pull-up transistor
approximately 150kΩ (VDD = 2.7 to 3.6V)
PG0/PWM0
to PG3/PWM3
PWM0 to PWM3
PG register
(Undefined after a reset)
PGSL register
("0" after a reset)
Internal data bus
1
MPX
0
RD
PG register write
Reset
SQ
R
Hi-Z
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXP973F064.PDF ] | |
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