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Número de pieza | HM62G18512 | |
Descripción | 8M Synchronous Fast Static RAM(512k-word x 18-bit) | |
Fabricantes | Hitachi Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de HM62G18512 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
No Preview Available ! HM62G18512 Series
8M Synchronous Fast Static RAM
(512k-word × 18-bit)
ADE-203-1185 (Z)
Preliminary
Rev. 0.0
Jun. 12, 2000
Description
The HM62G18512 is a synchronous fast static RAM organized as 512-kword × 18-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
• Power supply: 3.3 V +10%, –5%
• Clock frequency: 200 MHz to 250 MHz
• Internal self-timed late write
• Byte write control (2 byte write selects, one for each 9-bit)
• Optional ×36 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• User selective input trip-point
• Differential, HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single clock register-register mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
1 page HM62G18512 Series
Operation Table
ZZ SS G SWE SWEa SWEb K K Operation
DQ (n) DQ (n + 1)
H × × × × × × × sleep mode
High-Z High-Z
L H × × × × L-H H-L Dead
×
(not selected)
High-Z
L × H × × × × × Dead
High-Z High-Z
(Dummy read)
L L L H × × L-H H-L Read
× Dout
(a,b)0-8
L L × L L L L-H H-L Write a, b byte High-Z Din (a,b)0-8
L L × L L H L-H H-L Write a byte
High-Z Din (a)0-8
L L × L H L L-H H-L Write b byte
High-Z Din (b)0-8
Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs.
2. SWE, SS, SWEa to SWEb, SA are sampled at the rising edge of K clock.
3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or K) tied to VREF. Under such single-ended clock operation, all parameters
specified within this document will be met.
5
5 Page Timing Waveforms
Read Cycle-1
K
K
SA
SS
SWE
tKHKH
tKHKL tKLKH
tAVKH
tKHAX
A1 A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
SWEx
DQ
Note: G, ZZ = VIL
Do 0
tKHQX
Do 1
tKHQV
HM62G18512 Series
A4
Do 2
11
11 Page |
Páginas | Total 23 Páginas | |
PDF Descargar | [ Datasheet HM62G18512.PDF ] |
Número de pieza | Descripción | Fabricantes |
HM62G18512 | 8M Synchronous Fast Static RAM(512k-word x 18-bit) | Hitachi Semiconductor |
HM62G18512BP-4 | 8M Synchronous Fast Static RAM(512k-word x 18-bit) | Hitachi Semiconductor |
HM62G18512BP-5 | 8M Synchronous Fast Static RAM(512k-word x 18-bit) | Hitachi Semiconductor |
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