|
|
PDF ADG622 Data sheet ( Hoja de datos )
| Número de pieza | ADG622 | |
| Descripción | CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADG622 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
a
FEATURES
5.5 ⍀ (Max) On Resistance
0.9 ⍀ (Max) On-Resistance Flatness
2.7 V to 5.5 V Single Supply
؎2.7 V to ؎5.5 V Dual Supply
Rail-to-Rail Operation
10-Lead SOIC Package
Typical Power Consumption (<0.01 W)
TTL/CMOS Compatible Inputs
APPLICATIONS
Automatic Test Equipment
Power Routing
Communication Systems
Data Acquisition Systems
Sample and Hold Systems
Avionics
Relay Replacement
Battery-Powered Systems
CMOS ؎5 V/5 V
4 ⍀ Dual SPST Switches
ADG621/ADG622/ADG623
FUNCTIONAL BLOCK DIAGRAM
ADG621
ADG622
S1 S1
IN1 IN1
D1 D1
D2 D2
IN2 IN2
S2 S2
ADG623
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC "0" INPUT
GENERAL DESCRIPTION
The ADG621, ADG622, and the ADG623 are monolithic,
CMOS SPST (single-pole, single-throw) switches. Each switch
of the ADG621, ADG622, and ADG623 conducts equally well
in both directions when on.
The ADG621/ADG622/ADG623 contain two independent
switches. The ADG621 and ADG622 differ only in that both
switches are normally open and normally closed respectively. In the
ADG623, Switch 1 is normally open and Switch 2 is normally
closed. The ADG623 exhibits break-before-make switching action.
The ADG621/ADG622/ADG623 offers low on-resistance of
4 Ω, which is matched to within 0.25 Ω between channels.
These switches also provide low power dissipation yet gives
high switching speeds. The ADG621, ADG622, and ADG623
are available in a 10-lead µSOIC package.
PRODUCT HIGHLIGHTS
1. Low On Resistance (RON) (4 Ω typ)
2. Dual ± 2.7 V to ± 5.5 V or Single 2.7 V to 5.5 V
3. Low Power Dissipation. CMOS construction ensures low
power dissipation.
4. Tiny 10-Lead µSOIC Package
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
PIN CONFIGURATION
10-Lead SOIC
(RM-10)
S1 1
D1 2
IN2 3
ADG621/
ADG622/
ADG623
10 VDD
9 IN1
8 D2
GND 4 TOP VIEW 7 S2
(Not to Scale)
VSS 5
6 NC
NC = NO CONNECT
ADG621/ADG622/ADG623
VDD
VSS
GND
IDD
ISS
S
D
IN
RON
∆RON
RFLAT(ON)
IS (OFF)
ID (OFF)
ID, IS (ON)
VD (VS)
VINL
VINH
IINL(IINH)
CS (OFF)
CD (OFF)
CD, CS (ON)
tON
tOFF
tBBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
Insertion Loss
TERMINOLOGY
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied
to ground at the device.
Ground (0 V) Reference
Positive Supply Current
Negative Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic resistance between D and S.
On resistance match between any two Channels i.e., RON max – RON min.
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
Source Leakage Current with the switch “OFF.”
Drain Leakage Current with the switch “OFF.”
Channel Leakage Current with the switch “ON.”
Analog Voltage on Terminals D, S.
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Input Current of the Digital Input
“OFF” Switch Source Capacitance
“OFF” Switch Drain Capacitance
“ON” Switch Capacitance
Delay between applying the digital control input and the output switching on.
Delay between applying the digital control input and the output switching off.
“OFF” time or “ON” time measured between the 90% points of both switches, when switching from one
address state to another.
A measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
A measure of unwanted signal coupling through an “OFF” switch.
The frequency response of the “ON” switch.
The loss due to the ON resistance of the Switch.
REV. 0
–5–
5 Page 
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADG622.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADG620 | CMOS +-5 V/ +5V 4 OHM SINGLE SPDT SWITCHES | Analog Devices |
| ADG621 | CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES | Analog Devices |
| ADG622 | CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES | Analog Devices |
| ADG623 | CMOS +-5 V/ +5V 4 OHM DUAL SPST SWITCHES | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |