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ADG509F Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG509F
Beschreibung 4/8 Channel Fault-Protected Analog Multiplexers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
ADG509F Datasheet, Funktion
8-Channel/4-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F
FEATURES
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Low on resistance (270 Ω typical)
Fast switching times
tON: 230 ns maximum
tOFF: 130 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
Break-before-make construction
TTL and CMOS compatible inputs
APPLICATIONS
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
GENERAL DESCRIPTION
The ADG508F and ADG509F are CMOS analog multi-
plexers, with the ADG508F comprising eight single channels
and the ADG509F comprising four differential channels. These
multiplexers provide fault protection. Using a series n-channel,
p-channel, n-channel MOSFET structure, both device and signal
source protection is provided in the event of an overvoltage or
power loss. The multiplexer can withstand continuous overvolt-
age inputs from −40 V to +55 V. During fault conditions with
power supplies off, the multiplexer input (or output) appears as
an open circuit and only a few nanoamperes of leakage current
will flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
The ADG508F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG509F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used
to enable or disable the device. When disabled, all channels are
switched off.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAMS
ADG508F
S1
D
S8
1 OF 8
DECODER
A0 A1 A2 EN
Figure 1.
ADG509F
S1A
DA
S4A
S1B
S4B
1 OF 4
DECODER
DB
A0 A1 EN
Figure 2.
PRODUCT HIGHLIGHTS
1. Fault protection. The ADG508F/ADG509F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
2. On channel saturates while fault exists.
3. Low RON.
4. Fast switching times.
5. Break-before-make switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
6. Trench isolation eliminates latch-up. A dielectric trench
separates the p and n-channel MOSFETs thereby
preventing latch-up.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.






ADG509F Datasheet, Funktion
ADG508F/ADG509F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0 1
16 A1
EN 2
15 A2
VSS 3 ADG508F 14 GND
S1 4 TOP VIEW 13 VDD
S2 5 (Not to Scale) 12 S5
S3 6
11 S6
S4 7
10 S7
D8
9 S8
Figure 3. ADG508F Pin Configuration
Table 5. ADG508F Pin Function Descriptions
Pin No.
Mnemonic
Description
1 A0
Logic Control Input.
2 EN
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3 VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4 S1
Source Terminal 1. This pin can be an input or an output.
5 S2
Source Terminal 2. This pin can be an input or an output.
6 S3
Source Terminal 3. This pin can be an input or an output.
7 S4
Source Terminal 4. This pin can be an input or an output.
8D
Drain Terminal. This pin can be an input or an output.
9 S8
Source Terminal 8. This pin can be an input or an output.
10 S7
Source Terminal 7. This pin can be an input or an output.
11 S6
Source Terminal 6. This pin can be an input or an output.
12 S5
Source Terminal 5. This pin can be an input or an output.
13 VDD
Most Positive Power Supply Potential.
14 GND
Ground (0 V) Reference.
15 A2
Logic Control Input.
16 A1
Logic Control Input.
Rev. F | Page 6 of 20

6 Page









ADG509F pdf, datenblatt
ADG508F/ADG509F
TEST CIRCUITS
IDS
V1
S
VS
D
RON = V1/IDS
Figure 21. On Resistance
VDD
VSS
IS (OFF)
A
VS
VD
VDD
S1
S2
S8
VSS
D
EN 0.8V
Figure 22. IS (Off)
VDD
VSS
VDD
S1
S2
S8
VSS
D ID (OFF)
A
VD
EN 0.8V
VS
Figure 23. ID (Off)
NC S
ID (ON)
DA
NC = NO CONNECT
VD
Figure 24. ID (On)
VDD
VSS
A S1
S2
VDD
VSS
D
S8
VS
EN 0.8V
VD
Figure 25. Input Leakage Current (with Overvoltage)
0V 0V
VDD
VSS
0V A2
S1 A
VS
A1 ADG508F
A0
EN S8
D
GND
Figure 26. Input Leakage Current (with Power Supplies Off)
Rev. F | Page 12 of 20

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