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PDF ADG333 Data sheet ( Hoja de datos )
| Número de pieza | ADG333 | |
| Descripción | Quad SPDT Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADG333 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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FEATURES
44 V Supply Maximum Ratings
VSS to VDD Analog Signal Range
Low On Resistance (45 ⍀ max)
Low ∆RON (5 ⍀ max)
Low RON Match (4 ⍀ max)
Low Power Dissipation
Fast Switching Times
tON < 175 ns
tOFF < 145 ns
Low Leakage Currents (5 nA max)
Low Charge Injection (10 pC max)
Break-Before-Make Switching Action
APPLICATIONS
Audio and Video Switching
Battery Powered Systems
Test Equipment
Communication Systems
Quad SPDT Switch
ADG333A
FUNCTIONAL BLOCK DIAGRAM
S1A
D1
S1B
IN1
IN2
S2B
D2
S2A
ADG333A
S4A
D2
S4B
IN4
IN3
S3B
D3
S3A
SWITCHES SHOWN FOR A LOGIC “1” INPUT
GENERAL DESCRIPTION
The ADG333A is a monolithic CMOS device comprising four
independently selectable SPDT switches. It is designed on an
LC2MOS process which provides low power dissipation yet
achieves a high switching speed and a low on resistance.
The on resistance profile is very flat over the full analog input
range ensuring good linearity and low distortion when switching
audio signals. High switching speed also makes the part suitable
for video signal switching. CMOS construction ensures ultralow
power dissipation making the part ideally suited for portable,
battery powered instruments.
When they are ON, each switch conducts equally well in both
directions and has an input signal range which extends to the
power supplies. In the OFF condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent in
the design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG333A is fabricated on an enhanced LC2MOS
process, giving an increased signal range which extends
to the supply rails.
2. Low Power Dissipation
3. Low RON
4. Single Supply Operation
For applications where the analog signal is unipolar,
the ADG333A can be operated from a single rail power
supply. The part is fully specified with a single +12 V
supply.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
ADG333A
TERMINOLOGY
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
RON
∆RON
Ohmic resistance between D and S.
RON variation due to a change in the analog
input voltage with a constant load current.
RON Match
Difference between the RON of any two
channels.
IS (OFF)
Source leakage current with the switch
“OFF.”
ID (OFF)
Drain leakage current with the switch
“OFF.”
ID, IS (ON)
Channel leakage current with the switch
“ON.”
VD (VS)
CS (OFF)
CD (OFF)
Analog voltage on terminals D, S.
“OFF” Switch Source Capacitance.
“OFF” Switch Drain Capacitance.
CD, CS (ON)
tON
“ON” Switch Capacitance.
Delay between applying the digital control in-
put and the output switching on.
tOFF Delay between applying the digital control in-
put and the output switching off.
tOPEN
Break Before Make delay when switches are
configured as a multiplexer.
VINL
VINH
IINL (IINH)
Crosstalk
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
PIN CONFIGURATION
DIP/SOIC/SSOP
IN1 1
20 IN4
S1A 2
19 S4A
D1 3
18 D4
S1B 4
17 S4B
VSS 5 ADG333A 16 VDD
GND 6 TOP VIEW 15 NC
(Not to Scale)
S2B 7
14 S3B
D2 8
13 D3
S2A 9
12 S3A
IN2 10
11 IN3
NC = NO CONNECT
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ADG333.PDF ] | |
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