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PDF ADG3257 Data sheet ( Hoja de datos )
| Número de pieza | ADG3257 | |
| Descripción | 3.3 V/5 V Quad 2:1 Mux/Demux Bus Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
(4-Bit, 1 of 2) Bus Switch
ADG3257
FEATURES
100 ps propagation delay through the switch
2 Ω switches connect inputs to outputs
Data rates up to 933 Mbps
Single 3.3 V/5 V supply operation
Level translation operation
Ultralow quiescent supply current (1 nA typical)
3.5 ns switching
Switches remain in the off state when power is off
Standard 3257 type pinout
APPLICATIONS
Bus switching
Bus isolation
Level translation
Memory switching/interleaving
GENERAL DESCRIPTION
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low on
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional
ground bounce noise.
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table 1. These switches
are bidirectional when on. In the off state, signal levels are blocked
up to the supplies. When the power supply is off, the switches
remain in the off state, isolating Port A and Port B.
This bus switch is suited to both switching and level translation
applications. It can be used in applications requiring level trans-
lation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally,
with a diode connected in series with 5 V VDD, the ADG3257
may also be used in applications requiring 5 V to 3.3 V level
translation.
Table 1. Truth Table
BE S
HX
LL
LH
Function
Disable
A = B1
A = B2
FUNCTIONAL BLOCK DIAGRAM
1A 1B1
1B2
2A 2B1
2B2
3A 3B1
3B2
4A 4B1
4B2
LOGIC
BE S
Figure 1.
PRODUCT HIGHLIGHTS
1. 0.1 ns propagation delay through switch.
2. 2 Ω switches connect inputs to outputs.
3. Bidirectional operation.
4. Ultralow power dissipation.
5. 16-lead QSOP package.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
1 page  
ADG3257
VCC = 3.3 V ± 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage4
CAPACITANCE4
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS4
Propagation Delay A to B or B to A, tPD
Propagation Delay Matching6
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Select Time S to A or B
Enable
Disable
Maximum Data Rate
DIGITAL SWITCH
On Resistance
On-Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input4, 7
Symbol Conditions2
VINH
VINL
II 0 ≤ VIN ≤ 3.6 V
IOZ 0 ≤ A, B ≤ VCC
IOZ 0 ≤ A, B ≤ VCC
VP VIN = VCC = 3.3 V, IO = −5 μA
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
tPHL, tPLH5
tPZH, tPZL
tPHZ, tPLZ
VA = 0 V, CL = 50 pF
VA = 0 V, CL = 50 pF
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
tSEL_EN
tSEL_DIS
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
VA = 2 V p-p
RON
ΔRON
VA = 0 V, IO = 15 mA, 8 mA, TA = 25°C
VA= 0 V, Io = 15 mA, 8 mA
VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C
VA= 1 V, Io = 15 mA, 8 mA
VA = 0 V, IO = 15 mA, 8 mA
ICC Digital inputs = 0 V or VCC
ΔICC VCC = 3.3 V, one input at 3.0 V; others at VCC or GND
B Version
Min Typ3 Max Unit
2.0 V
−0.3 +0.8 V
±0.01 ±1 μA
±0.01 ±1 μA
±0.01 ±1 μA
2.3 2.6 2.8 V
7 pF
5 pF
11 pF
4 pF
0.10 ns
0.01 0.04 ns
1 5.5 9 ns
1 4.5 8.5 ns
8 12 ns
6 9 ns
933 Mbps
24
5
47
8
0.2
Ω
Ω
Ω
Ω
Ω
3.0 5.5 V
0.001 1
μA
200 μA
1 Temperature range is: Version B: −40°C to +85°C.
2 See Test Circuits section.
3 All typical values are at TA = 25°C, unless otherwise noted.
4 Guaranteed by design, not subject to production test.
5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.
7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute
no significant ac or dc currents as they transition.
Rev. E | Page 4 of 12
5 Page 
ADG3257
APPLICATIONS INFORMATION
MIXED VOLTAGE OPERATION, LEVEL TRANSLATION
Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3.3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
as shown in Figure 15.
VCC = 5V
BE
3.3V CPU/DSP/
MICROPROCESSOR/
MEMORY
5V MEMORY
5V I/O
3.3V
5V
3.3V
3.3V
Figure 15. Level Translation Between 5 V and 3.3 V Devices
The diode drops the internal gate voltage down to 4.3 V. The
bus switch limits the voltage present on the output to
VCC − External Diode Drop = VTH
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V, the
output voltage is limited to 3.3 V with a logic high.
VOUT
3.3V
5V SUPPLY
0V
SWITCH
5V VIN
INPUT
Figure 16. Input Voltage to Output Voltage
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need for
an external diode. The internal VTH drop is 1 V, so with a
VCC = 3.3 V the bus switch limits the output voltage to
VCC − 1 V = 2.3 V
3.3V
VOUT
2.5V
3.3V
2.5V
ADG3257
3.3V SUPPLY
2.5V
2.5V
0V
SWITCH
3.3V VIN
INPUT
Figure 17. 3.3 V to 2.5 V Level Translation Using the ADG3257 Bus Switch
MEMORY SWITCHING
This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 18 illustrates the
ADG3257 in such an application.
SDRAM NO. 1
SDRAM NO. 2
SDRAM NO. 7
SDRAM NO. 8
LOGIC
BE S
Figure 18. Allows Additional Memory Modules Without Added Drive or Delay
Rev. E | Page 10 of 12
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADG3257.PDF ] | |
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