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Teilenummer | ADG3245 |
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Beschreibung | 2.5 V/3.3 V / 8-Bit 2-Port Level Translating / Bus Switch | |
Hersteller | Analog Devices | |
Logo | ||
Gesamt 13 Seiten 2.5 V/3.3 V, 8-Bit, 2-Port
Level Translating, Bus Switch
ADG3245
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
20-Lead TSSOP and LFCSP Packages
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
GENERAL DESCRIPTION
The ADG3245 is a 2.5 V or 3.3 V, 8-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
The switches are enabled by means of the bus enable (BE) input
signal. These digital switches allow bidirectional signals to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
VCC is reduced internally, allowing for level translation between
3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
FUNCTIONAL BLOCK DIAGRAM
A0 B0
A7 B7
BE
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation
2. Extremely low propagation delay through switch
3. 4.5 W switches connect inputs to outputs
4. Level/voltage translation
5. 20-lead TSSOP and LFCSP (4 mm ¥ 4 mm) packages
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
40
35 TA = 25؇C
SEL = VCC
30
VCC = 3V
25
VCC = 3.3V
20
15
10 VCC = 3.6V
5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VA/VB – V
TPC 1. On Resistance vs.
Input Voltage
Typical Performance Characteristics–ADG3245
40
35 TA = 25؇C
SEL = VCC
30
VCC = 2.3V
25
VCC = 2.5V
20
15
VCC = 2.7V
10
5
0
0 0.5 1.0 1.5 2.0 2.5
VA/VB – V
TPC 2. On Resistance vs.
Input Voltage
3.0
40
35 TA = 25؇C
SEL = 0V
30
VCC = 3V
25
VCC = 3.3V
20
15
VCC = 3.6V
10
5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VA/VB – V
TPC 3. On Resistance vs.
Input Voltage
20
VCC = 3.3V
SEL = VCC
15
10
؉85؇C
5 ؉25؇C
؊40؇C
0
0 0.5 1.0 1.5 2.0
VA/VB – V
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
15
VCC = 2.5V
SEL = VCC
10
؉85؇C
5
؊40؇C
؉25؇C
0
0 0.5 1.0 1.2
VA/VB – V
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
3.0
TA = 25؇C
2.5
SEL = VCC
IO = –5A
2.0
1.5
VCC = 3.6V
VCC = 3.3V
VCC = 3V
1.0
0.5
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC – V
TPC 6. Pass Voltage vs. VCC
2.5
TA = 25؇C
SEL = VCC
2.0 IO = –5A
1.5
1.0
VCC = 2.7V
VCC = 2.5V
VCC = 2.3V
0.5
0
0 0.5 1.0 1.5 2.0 2.5 3.0
VCC – V
TPC 7. Pass Voltage vs. VCC
2.5
TA = 25؇C
SEL = 0V
2.0 IO = –5A
1.5
1.0
VCC = 3.6V
VCC = 3.3V
VCC = 3V
0.5
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC – V
TPC 8. Pass Voltage vs. VCC
1800
1600
TA = 25؇C
1400
1200
1000
VCC = 3.3V, SEL = 0V
800
600
400 VCC = SEL = 3.3V
200 VCC = SEL = 2.5V
0
0 2 4 6 8 10 12 14 16 18 20
ENABLE FREQUENCY – MHz
TPC 9. ICC vs. Enable Frequency
REV.$
–5–
6 Page OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
4.10
4.00 SQ
3.90
TOP VIEW
0.50
BSC
0.30
0.25
0.18
16
15
20
1
EXPOSED
PAD
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
11 5
0.65
0.60
10 6
BOTTOM VIEW
0.20 MIN
0.55
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 12. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
6.60
6.50
6.40
20 11
4.50
4.40
4.30
6.40 BSC
1 10
PIN 1
0.15
0.05
0.65
BSC
0.30
COPLANARITY 0.19
0.10
1.20 MAX
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 13. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
0.75
0.60
0.45
ADG3245
REV. C
–11–
12 Page | ||
Seiten | Gesamt 13 Seiten | |
PDF Download | [ ADG3245 Schematic.PDF ] |
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