Datenblatt-pdf.com


ADF4206 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4206
Beschreibung Dual RF PLL Frequency Synthesizers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
ADF4206 Datasheet, Funktion
Dual RF PLL Frequency Synthesizers
ADF4206/ADF4208
FEATURES
ADF4206: 550 MHz/550 MHz
ADF4208: 2.0 GHz/1.1 GHz
2.7 V to 5.5 V power supply
Selectable charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Selectable charge pump currents
On-chip oscillator circuit
Selectable dual modulus prescaler
RF2: 32/33 or 64/65
RF1: 32/33 or 64/65
3-wire serial interface
Power-down mode
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base stations for wireless radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Communications test equipment
CATV equipment
GENERAL DESCRIPTION
The ADF420x family of dual frequency synthesizers are used
to implement local oscillators in the upconversion and down-
conversion sections of wireless receivers and transmitters. Each
synthesizer consists of a low noise, digital, phase frequency detector
(PFD); a precision charge pump; a programmable reference
divider; programmable A and B counters; and a dual modulus
prescaler (P/P + 1). The A (6-bit) and B (11-bit) counters, in
conjunction with the dual modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. The on-chip oscillator circuitry allows the reference
input to be derived from crystal oscillators.
A complete phase-locked loop (PLL) can be implemented if the
synthesizers are used with an external loop filter and voltage
controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
RF2INA
RF2INB
OSCIN
OSCOUT
CLK
DATA
LE
RF1INA
RF1INB
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
VP1
VP2
N = BP + A
RF2
PRESCALER
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
N = BP + A
RF1
PRESCALER
11-BIT RF2
B-COUNTER
6-BIT RF2
A-COUNTER
14-BIT RF2
R-COUNTER
14-BIT RF1
R-COUNTER
11-BIT RF1
B-COUNTER
6-BIT RF1
A-COUNTER
ADF4206/ADF4208
PHASE
COMPARATOR
RF2
LOCK
DETECT
CHARGE
PUMP
CPRF2
OUTPUT
MUX
MUXOUT
RF1
LOCK
DETECT
PHASE
COMPARATOR
CHARGE
PUMP
CPRF1
DGNDRF1
AGNDRF1 DGNDRF2
Figure 1.
AGNDRF2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADF4206 Datasheet, Funktion
ADF4206/ADF4208
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.1
Table 3.
Parameter
VDD1 to GND2
VDD1 to VDD2
VP1, VP2 to GND
VP1, VP2 to VDD1
Digital I/O Voltage to GND
Analog I/O Voltage to GND
OSCIN, OSCOUT, RF1IN (A, B),
RF2IN (A, B) to GND
RFINA to RFINB (RF1, RF2)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
Reflow Soldering
Peak Temperature (40 sec)
Ratings
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to DVDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−65°C to +150°C
150°C
112°C/W
30.4°C/W
260°C
1 This device is a high performance RF integrated circuit with an ESD rating of
<2 kΩ and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
2 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TRANSISTOR COUNT
11,749 (CMOS) and 522 (Bipolar).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24

6 Page









ADF4206 pdf, datenblatt
ADF4206/ADF4208
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 25 is a simplified
schematic.
HI
UP
D1 Q1
VP
CHARGE
PUMP
U1
R DIVIDER
CLR1
DELAY
ELEMENT
U3
CP
HI
N DIVIDER
CLR2
DOWN
D2 Q2
U2
CPGND
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 25. PFD Simplified Schematic and Timing (In Lock)
The PFD includes a delay element that sets the width of the
antibacklash phase. The typical value for this in the ADF420x
family is 3 ns. The pulse ensures that there is no dead zone in
the PFD transfer function and minimizes phase noise and
reference spurs.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4206 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Figure 28
and Figure 30. Figure 26 shows the MUXOUT circuit in block
diagram form.
DVDD
RF2 ANALOG LOCK DETECT
RF2 R COUNTER OUTPUT
RF2 N COUNTER OUTPUT
RF2/RF1 ANALOG LOCK DETECT
RF1 R COUNTER OUTPUT
RF1 N COUNTER OUTPUT
RF1 ANALOG LOCK DETECT
MUX
CONTROL
MUXOUT
Figure 26. MUXOUT Circuit
DGND
LOCK DETECT
MUXOUT can be programmed for analog lock detect. The
N-channel open-drain analog lock detect is operated with an
external pull-up resistor of 10 kΩ nominal. When lock is
detected, it is high with narrow, low going pulses.
INPUT SHIFT REGISTER
The functional block diagram for the ADF420x family is shown
in Figure 1. The main blocks include a 22-bit input shift register,
a 14-bit R counter, and a 17-bit N counter, comprising a 6-bit
A counter and an 11-bit B counter. Data is clocked into the
22-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs (DB1, DB0) as
shown in the timing diagram of Figure 2.
Table 5 is the truth table for these bits.
Table 5. C2, C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 RF2 R counter
0 1 RF2 AB counter (and prescaler select)
1 0 RF1 R counter
1 1 RF1 AB counter (and prescaler select)
Rev. A | Page 12 of 24

12 Page





SeitenGesamt 24 Seiten
PDF Download[ ADF4206 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADF4206Dual RF PLL Frequency SynthesizersAnalog Devices
Analog Devices
ADF4207Dual RF PLL Frequency SynthesizersAnalog Devices
Analog Devices
ADF4208Dual RF PLL Frequency SynthesizersAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche