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ADF4106 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4106
Beschreibung PLL Frequency Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADF4106 Datasheet, Funktion
Data Sheet
PLL Frequency Synthesizer
ADF4106
FEATURES
GENERAL DESCRIPTION
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
Broadband wireless access
Satellite systems
Instrumentation
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
Wireless LANS
Base stations for wireless radios
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER 22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4106
Figure 1.
Rev. F
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Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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ADF4106 Datasheet, Funktion
Data Sheet
t3 t4
CLOCK
DATA DB23 (MSB)
LE
LE
t1 t2
DB22
DB2
DB1 (CONTROL
BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
ADF4106
Rev. F | Page 5 of 24

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ADF4106 pdf, datenblatt
Data Sheet
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the
phase and frequency difference between them. Figure 20 is a
simplified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the reference counter latch, ABP2 and ABP1, control the
width of the pulse. See Table 7.
HI
R DIVIDER
D1 Q1 UP
U1
CLR1
VP
CHARGE
PUMP
PROGRAMMABLE
DELAY
ABP2 ABP1
U3
CP
CLR2 DOWN
HI D2 Q2
N DIVIDER
U2
CPGND
Figure 20. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4106 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 21 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector cycles is less than
15 ns. With LDP set to 1, five consecutive cycles of less than
15 ns are required to set the lock detect. It stays set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
ADF4106
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock is detected, this output is high with narrow, low-
going pulses.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL
MUXOUT
Figure 21. MUXOUT Circuit
DGND
INPUT SHIFT REGISTER
The ADF4106 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of Figure 2. The truth table for
these bits is shown in Table 5. Table 6 shows a summary of how
the latches are programmed.
Table 5. C1, C2 Truth Table
Control Bits
C2 C1 Data Latch
0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch
Rev. F | Page 11 of 24

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