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ADE7751AN Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADE7751AN
Beschreibung Energy Metering IC with On-Chip Fault Detection
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADE7751AN Datasheet, Funktion
a
Energy Metering IC
with On-Chip Fault Detection
ADE7751*
FEATURES
High Accuracy, Surpasses 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error over a Dynamic Range of 500 to 1
Supplies Average Real Power on the Frequency
Outputs F1 and F2
High-Frequency Output CF Is Intended for Calibration
and Supplies Instantaneous Real Power
Continuous Monitoring of the Phase and Neutral
Current Allows Fault Detection in 2-Wire
Distribution Systems
ADE7751 Uses the Larger of the Two Currents (Phase
or Neutral) to Bill—Even During a Fault Condition
Two Logic Outputs (FAULT and REVP) Can Be Used to
Indicate a Potential Miswiring or Fault Condition
Direct Drive for Electromechanical Counters and
2-Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of Shunt and Burden Resistance
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ؎ 8% (30 ppm/؇C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low-Cost CMOS Process
GENERAL DESCRIPTION
The ADE7751 is a high-accuracy, fault-tolerant electrical energy
measurement IC that is intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard.
The only analog circuitry used in the ADE7751 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The ADE7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the ADE7751 to continue
accurate billing during a fault event. The ADE7751 does this
by continuously monitoring both the phase and neutral (return)
currents. A fault is indicated when these currents differ by more
than 12.5%. Billing is continued using the larger of the two currents.
The ADE7751 supplies average real power information on the
low-frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration purposes.
The ADE7751 includes a power supply monitoring circuit on the
AVDD supply pin. The ADE7751 will remain in a reset condition
until the supply voltage on AVDD reaches 4 V. If the supply falls
below 4 V, the ADE7751 will also be reset and no pulses will be
issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are matched whether the HPF in Channel 1 is
on or off. The ADE7751 also has anticreep protection.
The ADE7751 is available in 24-lead DIP and SSOP packages.
FUNCTIONAL BLOCK DIAGRAM
G0 G1
AVDD AGND
FAULT
AC/DC DVDD DGND
V1A
V1N
V1B
V2P
V2N
ADE7751
POWER
SUPPLY MONITOR
SIGNAL
A< >B
...110101... A
PROCESSING
BLOCK
ADC
HPF
PGA
A >B
؋1, ؋2, ؋8, ؋16
ADC
PGA
؋1, ؋2, ؋8, ؋16
...110101... B
B>A
PHASE
CORRECTION
MULTIPLIER
LPF
. . .11011001. . .
ADC
2.5V
4k
REFERENCE
DIGITAL-TO-FREQUENCY
CONVERTER
REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2 RESET
*US Patent 5,745,323; 5,760,617; 5,862,069; 5,872,469.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






ADE7751AN Datasheet, Funktion
ADE7751
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic
13, 14 S1, S0
15, 16
17
G1, G0
CLKIN
18 CLKOUT
19 FAULT
20 REVP
21 DGND
22
23, 24
CF
F2, F1
Description
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Select-
ing a Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8, and 16. See Analog Inputs section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the ADE7751. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF
and 33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the ADE7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN or by the gate oscillator circuit.
This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset
to zero when a fault condition is no longer detected. See Fault Detection section.
This logic output will go logic high when negative power is detected, i.e., when the phase angle
between the voltage and current signals is greater that 90°. This output is not latched and will be
reset when positive power is once again detected. The output will go high or low at the same time as
a pulse is issued on CF.
This provides the ground reference for the digital circuitry in the ADE7751, i.e., multiplier, filter,
and digital-to-frequency converter. This pin should be tied to the analog ground plane of the PCB.
The digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical
and digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane
should only be connected to the digital ground plane at one point, e.g., a star ground.
Calibration Frequency Logic Output. The CF logic output gives instantaneous real power informa-
tion. This output is intended to be used for calibration purposes. Also see SCF pin description.
Low-Frequency Logic Outputs. F1 and F2 supply average real power information. The logic
outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See
Transfer Function section.
TERMINOLOGY
ADC Offset Error
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see an analog input signal of 1 mV to
10 mV. However, when the HPF is switched on, the offset is
removed from the current channel and the power calculation is
not affected by this offset.
Gain Error
The gain error of the ADE7751 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel
V1A. The difference is expressed as a percentage of the ideal
frequency. The ideal frequency is obtained from the transfer
function—see Transfer Function section.
Gain Error Match
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output
frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from
1 to 2, 8, or 16.
Measurement Error
The error associated with the energy measurement made by the
ADE7751 is defined by the following formula:
Percentage Error =
Energy Registered by the ADE7751 – True Energy × 100%
True Energy
Phase Error Between Channels
The HPF (high-pass filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels, a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within ± 0.1° over a range of 45 Hz to 65 Hz and ± 0.2°
over a range 40 Hz to 1 kHz (see Figures 10 and 11).
Power Supply Rejection
This quantifies the ADE7751 measurement error as a percent-
age of reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of the reading—see Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied ± 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.
–6– REV. 0

6 Page









ADE7751AN pdf, datenblatt
ADE7751
Figure 7 shows two typical connections for Channel V2. The first
option uses a PT (potential transformer) to provide complete isola-
tion from the mains voltage. In the second option, the ADE7751
is biased around the neutral wire and a resistor divider is used to
provide a voltage signal that is proportional to the line voltage.
Adjusting the ratio of Ra and Rb is also a convenient way of
carrying out a gain calibration on the meter.
CT Rf
PHASE NEUTRAL
؎660mV
Rf
AGND
V2P
Cf V2N
Cf
Ra Cf
Rb
؎660mV
VR
V2P
Rf V2N
PHASE NEUTRAL
NOTE
Ra Rf;
Rb + VR = Rf
Cf
Figure 7. Typical Connections for Channel 2
POWER SUPPLY MONITOR
The ADE7751 contains an on-chip power supply monitor. The
analog supply (AVDD) is continuously monitored by the ADE7751.
If the supply is less than 4 V ± 5%, the ADE7751 will be reset.
This is useful to ensure correct device start up at power-up and
power-down. The power supply monitor has built-in hysteresis
and filtering. This gives a high degree of immunity to false
triggering due to noisy supplies.
As can be seen in Figure 8, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about ±5%. The power supply
and decoupling for the part should be such that the ripple at AVDD
does not exceed 5 V ± 5% as specified for normal operation.
AVDD
5V
4V
0V
INTERNAL
RESET RESET
TIME
ACTIVE
RESET
Figure 8. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 9 shows the effect of offsets on the real power calculation. As
shown in Figure 9, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the real
power information, the offsets will have contributed a constant
error to the real power calculation. This problem is easily avoided by
enabling the HPF (i.e., pin AC/DC is set logic high) in Channel 1.
By removing the offset from at least one channel, no error component
can be generated at dc by the multiplication. Error terms at cos(ωt)
are removed by the LPF and the digital-to-frequency conversion—
see Digital-to-Frequency Conversion section.
( ) ( )Vcos(ωt) + VOS × I × cos(ωt) + IOS =
V ×I
2
+ VOS
× IOS
+ VOS
×I
× cos(ωt)
+V
× IOS
×
cos(ωt )
+
V
×
2
I
× cos(2ωt)
VOS ؋ IOS
V؋I
2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
IOS ؋ V
VOS ؋ I
0 2
FREQUENCY – RAD/S
Figure 9. Effect of Channel Offsets on the
Real Power Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 10 and 11 show the phase error between chan-
nels with the compensation network activated. The ADE7751
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low-power factors.
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY – Hz
Figure 10. Phase Error Between Channels (0 Hz to 1 kHz)
–12–
REV. 0

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