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ADC78H90CIMT Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC78H90CIMT
Beschreibung 8-Channel/ 500 kSPS/ 12-Bit A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 15 Seiten
ADC78H90CIMT Datasheet, Funktion
February 2004
ADC78H90
8-Channel, 500 kSPS, 12-Bit A/D Converter
General Description
The ADC78H90 is a low-power, eight-channel CMOS 12-bit
analog-to-digital converter with a conversion throughput of
500 kSPS. The converter is based on a successive-
approximation register architecture with an internal track-
and-hold circuit. It can be configured to accept up to eight
input signals at inputs AIN1 through AIN8.
The output serial data is straight binary, and is compatible
with several standards, such as SPI, QSPI, MICROW-
IRE, and many common DSP serial interfaces.
The ADC78H90 may be operated with independent analog
and digital supplies. The analog supply (AVDD) can range
from +2.7V to +5.25V, and the digital supply (DVDD) can
range from +2.7V to AVDD. Normal power consumption using
a +3V or +5V supply is 1.5 mW and 8.3 mW, respectively.
The power-down feature reduces the power consumption to
just 0.3 µW using a +3V supply, or 0.5 µW using a +5V
supply.
The ADC78H90 is packaged in a 16-lead TSSOP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Features
n Eight input channels
n Variable power management
n Independent analog and digital supplies
n SPI/QSPI/MICROWIRE/DSP compatible
n Packaged in 16-lead TSSOP
Key Specifications
n Conversion Rate
n DNL
n INL
n Power Consumption
— 3V Supply
— 5V Supply
500 kSPS
± 1 LSB (max)
± 1 LSB (max)
1.5 mW (typ)
8.3 mW (typ)
Applications
n Automotive Navigation
n Portable Systems
n Medical Instruments
n Mobile Communications
n Instrumentation and Control Systems
Connection Diagram
Ordering Information
Order Code
ADC78H90CIMT
ADC78H90CIMTX
ADC78H90EVAL
Temperature Range
−40˚C to +85˚C
−40˚C to +85˚C
20079305
Description
16-Lead TSSOP Package
16-Lead TSSOP Package, Tape & Reel
Evaluation Board
TRI-STATE® is a trademark of National Semiconductor Corporation.
MICROWIREis a trademark of National Semiconductor Corporation.
QSPIand SPIare trademarks of Motorola, Inc.
© 2004 National Semiconductor Corporation DS200793
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ADC78H90CIMT Datasheet, Funktion
Timing Diagrams
Timing Test Circuit
20079308
ADC78H90 Serial Timing Diagram
20079306
20079350
SCLK and CS Timing Parameters
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ADC78H90CIMT pdf, datenblatt
Applications Information (Continued)
FIGURE 3. ADC78H90 Timing Diagram
20079351
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is
active when CS is low. Thus, CS acts as an output enable.
Additionally, the device goes into a power down state when
CS is high.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK
cycles the conversion is accomplished and the data is
clocked out, MSB first. That is, for rising edges 1 through 3
after the fall of CS, the ADC is in the track mode and for
rising edges 4 through 16 a conversion is performed and the
data is clocked out. If there are more than one conversion in
a frame, the ADC will re-enter the track mode on the falling
edge of SCLK after the N*16th rising edge of SCLK, and
re-enter the hold/convert mode on the N*16+4th rising edge
of SCLK, where "N" must be an integer.
When CS is brought high, SCLK is internally gated off. If
SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the
internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of
SCLK. If SCLK is stopped with SCLK high, the ADC enters
the track mode on the first falling edge of SCLK after the
falling edge of CS.
During each conversion, data is clocked into the DIN pin on
the first 8 rising edges of SCLK after the fall of CS. For each
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See Tables 1, 2, 3
The first conversion after power up is meaningless informa-
tion and should be ignored.
If CS and SCLK go low simultaneously, it is the following
rising edge of SCLK that is considered the first rising edge
for clocking data into DIN.
TABLE 1. Control Register Bits
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
Bit #:
7, 6, 2, 1, 0
5
4
3
Symbol:
DONTC
ADD2
ADD1
ADD0
TABLE 2. Control Register Bit Descriptions
Description
Don’t care. The value of these bit do not affect the device.
These three bits determine which input channel will be sampled and
converted on the next falling edge of CS. The mapping between codes and
channels is shown in Table 3.
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