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ADC7802 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADC7802
Beschreibung Autocalibrating/ 4-Channel/ 12-Bit ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 13 Seiten
ADC7802 Datasheet, Funktion
® ADC7802
Autocalibrating, 4-Channel, 12-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q TOTAL UNADJUSTED ERROR 1/2LSB
OVER FULL TEMPERATURE RANGE
q FOUR-CHANNEL INPUT MULTIPLEXER
q LOW POWER: 10mW plus Power Down
Mode
q SINGLE SUPPLY: +5V
q FAST CONVERSION TIME: 8.5µs Including
Acquisition
q AUTOCAL: No Offset or Gain Adjust
Required
q UNIPOLAR INPUTS: 0V to 5V
q MICROPROCESSOR-COMPATIBLE
INTERFACE
q INTERNAL SAMPLE/HOLD
DESCRIPTION
The ADC7802 is a monolithic CMOS 12-bit A/D
converter with internal sample/hold and four-channel
multiplexer. An autocalibration cycle, occurring auto-
matically at power on, guarantees a total unadjusted
error within ±1/2LSB over the specified temperature
range, eliminating the need for offset or gain adjust-
ment. The 5V single-supply requirements and stan-
dard CS, RD, and WR control signals make the part
very easy to use in microprocessor applications. Con-
version results are available in two bytes through an 8-
bit three-state output bus.
The ADC7802 is available in a 28-pin plastic DIP and
28-lead PLCC, fully specified for operation over the
industrial –40°C to +85°C temperature range.
CS
A0
Address
Latch and
Calibration
Microcontroller
Clock
Control
RD
A1 Decoder and Memory
Logic
WR
SFR
AIN0
AIN1
AIN2
AIN3
Analog
Multiplexer
Capacitor Array
Sampling ADC
VREF +
VREF
Three-State
Input/Output
BUSY
8-Bit
Data Bus
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1050B
Printed in U.S.A. June, 1993






ADC7802 Datasheet, Funktion
THEORY OF OPERATION
ADC7802 uses the advantages of advanced CMOS technol-
ogy (logic density, stable capacitors, precision analog
switches, and low power consumption) to provide a precise
12-bit analog-to-digital converter with on-chip sampling and
four-channel analog-input multiplexer.
The input stage consists of an analog multiplexer with an
address latch to select from four input channels.
The converter stage consists of an advanced successive
approximation architecture using charge redistribution on a
capacitor network to digitize the input signal. A temperature-
stabilized differential auto-zeroing circuit is used to mini-
mize offset errors in the comparator. This allows offset errors
to be corrected during the acquisition phase of each conver-
sion cycle.
Linearity errors in the binary weighted main capacitor net-
work are corrected using a capacitor trim network and
correction factors stored in on-chip memory. The correction
terms are calculated by a microcontroller during a calibration
cycle, initiated either by power-up or by applying an external
calibration signal at any time. During conversion, the correct
trim capacitors are switched into the main capacitor array as
needed to correct the conversion accuracy. This is faster than
a complex digital error correction system, which could slow
down the throughput rate. With all of the capacitors in both
the main array and the trim array on the same chip, excellent
stability is achieved, both over temperature and over time.
For flexibility, timing circuits include both an internal clock
generator and an input for an external clock to synchronize
with external systems. Standard control signals and three-
state input/output registers simplify interfacing ADC7802 to
most micro-controllers, microprocessors or digital storage
systems.
Finally, this performance is matched with the low-power
advantages of CMOS structures to allow a typical power
consumption of 10mW.
0-5V
Input
NC 1
2
3
4
SFR
AIN0
AIN1
AIN2
VA
28
10nF
AGND 27
CAL 26 NC
A1 25
+5V
+
10µF
100k
+5V
+
10µF
5
6
10nF
7
8
AIN3
A0 24
VREF+
CLK 23
VREF– BUSY 22
DGND HBE 21
BUSY
9 VD
Data Bit 7 10 D7
WR 20
CS 19
BUSY
High Byte
Enable Command
Convert Command
LOW Data Bit 6 11 D6
LOW Data Bit 5 12 D5
LOW Data Bit 4 13 D4
Data Bit 11
(MSB)
Data Bit 3
14
D3
RD 18
Read Command
Data Bit 0
D0 17 (LSB) Data Bit 8
D1 16 Data Bit 1 Data Bit 9
D2 15 Data Bit 2 Data Bit 10
HBE Input HBE Input
HIGH
LOW
HBE Input HBE Input
LOW
HIGH
FIGURE 1. Basic Operation.
Figures 2 and 3 show the full conversion sequence and the
timing to initiate a conversion.
CALIBRATION
A calibration cycle is initiated automatically upon power-up
(or after a power failure). Calibration can also be initiated by
the user at any time by the rising edge of a minimum 100ns-
wide LOW pulse on the CAL pin (pin 26), or by setting D1
HIGH in the Special Function Register (see SFR section). A
calibration command will initiate a calibration cycle, regard-
less of whether a conversion is in process. During a calibra-
tion cycle, convert commands are ignored.
OPERATION
Calibration takes 168 clock cycles, and a normal conversion
(17 clock cycles) is added automatically. For maximum
BASIC OPERATION
Figure 1 shows the simple circuit required to operate
ADC7802 in the Transparent Mode, converting a single
input channel. A convert command on pin 20 (WR) starts a
conversion. Pin 22 (BUSY) will output a LOW during the
conversion process (including sample acquisition and con-
accuracy, the supplies and reference need to be stable during
the calibration procedure. To ensure that supply voltages and
reference voltages have settled and are stable, an internal
timer provides a waiting period of 42,425 clock cycles
between power-up/power-failure and the start of the calibra-
tion cycle.
version), and rises only after the conversion is completed.
The two bytes of output data can then be read using pin 18
(RD) and pin 21 (HBE).
READING DATA
Data from the ADC7802 is read in two 8-bit bytes, with the
Low byte containing the 8 LSBs of data, and the High byte
STARTING A CONVERSION
containing the 4 MSBs of data. The outputs are coded in
straight binary (with 0V = 000 hex, 5V = FFF hex), and the
A conversion is initiated on the rising edge of the WR input,
with valid signals on A0, A1 and CS. The selected input
channel is sampled for five clock cycles, during which the
comparator offset is also auto-zeroed to below 1/4LSB of
error. The successive approximation conversion takes place
data is presented in a right-justified format (with the LSB as
the most right bit in the 16-bit word). Two read operations are
required to transfer the High byte and Low byte, and the
bytes are presented according to the input level on the High
Byte Enable pin (HBE).
during clock cycles 6 through 17.
®
ADC7802
6

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ADC7802 pdf, datenblatt
The clock generator can operate between 100kHz and 2MHz.
With R = 100k, the clock frequency will nominally be
800kHz. The internal clock oscillators may vary by up to
20% from device to device, and will vary with temperature,
as shown in the typical performance curves. Therefore, use
of an external clock source is preferred in many applications
where control of the conversion timing is critical, or where
multiple converters need to be synchronized.
APPLICATIONS
BIPOLAR INPUT RANGES
Figure 12 shows a circuit to accurately and simply convert a
bipolar ±5V input signal into a unipolar 0 to 5V signal for
conversion by the ADC7802, using a precision, low-cost
complete difference amplifier, INA105.
INA105
25k
25k
2
5
±5V 1
Input
25k
25k
3
+5V (VREF+)
FIGURE 12. ±5V Input Range.
0 to 5V
6 to ADC7802
Figure 13 shows a circuit to convert a bipolar ±10V input
signal into a unipolar 0 to 5V signal for conversion by the
ADC7802. The precision of this circuit will depend on the
matching and tracking of the three resistors used.
±10V
Input
+5V
(V +)
REF
R2
R1
5k
OPA27
10k
R3 10k
0 to 5V
to ADC7802
FIGURE 13. ±10V Input Range.
To trim this circuit for full 12-bit precision, R2 and R3 need
to be adjustable over appropriate ranges. To trim, first have
the ADC7802 converting continually and apply +9.9927V
(+10V – 1.5LSB) at the input. Adjust R3 until the ADC7802
output toggles between the codes FFE hex and FFF hex. This
makes R3 extremely close to R1. Then, apply –9.9976V (–10V
+ 0.5LSB) at the input, and adjust R2 until the ADC7802
output toggles between 000 hex and 001 hex. At each trim
point, the current through the third resistor will be almost
zero, so that one trim iteration will be enough in most cases.
More iterations may be required if the op amp selected has
large offset voltage or bias currents, or if the +5V reference
is not precise.
This circuit can also be used to adjust gain and offset errors
due to the components preceding the ADC7802, to match the
performance of the self-calibration provided by the con-
verter.
INTERFACING TO MOTOROLA
MICROPROCESSORS
Figure 14 shows a typical interface to Motorola microproces-
sors, while Figure 15 shows how the result can be placed in
register D0.
A1 - A23
(A0 - A19)
MC68000
(MC68008)
AS
DACK
R/W
Address Bus
A1
INT
Address ADC_CS
Decoder
Logic
HBE SFR BUSY
CS
RD
DO 0 - DO 7 DO 0
WR
ADC7802
DO 1 D0 - D7
A1
A0
FIGURE 14. Interface to Motorola Microprocessors.
Conversion is initiated by a write instruction decoded by the
address decoder logic, with the lower two bits of the address
bus selecting an ADC input channel, as follows:
MOVE.W D0, ADC-ADDRESS
The result of the conversion is read from the data bus by a
read instruction to ADC-ADDRESS as follows:
MOVEP.W $000 (ADC-ADDRESS), D0
This puts the 12-bit conversion result in the DO register, as
shown in Figure 15. The address decoder must pull down
ADC_CS at ADC-ADDRESS to access the Low byte and
ADC-ADDRESS +2 to access the High byte.
INTERFACING TO INTEL MICROPROCESSORS
Figure 16 shows a typical interface to Intel.
A conversion is initiated by a write instruction to address
ADC_CS. Data pins DO0 and DO1 select the analog input
channel. The BUSY signal can be used to generate a micro-
processor interrupt (INT) when the conversion is completed.
A read instruction from the ADC_CS address fetches the
Low byte, and a read instruction from the ADC_CS address
+2 fetches the High byte.
®
ADC7802
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