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PDF ADC71KG Data sheet ( Hoja de datos )
| Número de pieza | ADC71KG | |
| Descripción | 16-Bit ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADC71
16-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 16-BIT RESOLUTION
q ±0.003% MAXIMUM NONLINEARITY
q COMPACT DESIGN: 32-pin Hermetic
Ceramic Package
q CONVERSION SPEED: 50µs max
DESCRIPTION
The ADC71 is a low cost, high quality, 16-bit succes-
sive approximation analog-to-digital converter. It uses
laser-trimmed ICs and is packaged in a convenient
32-pin hermetic ceramic dual-in-line package. The
converter is complete with internal reference, clock,
comparator, and thin-film scaling resistors, which
allow selection of analog input ranges of ±2.5V, ±5V,
±10V, 0 to +5V, 0 to +10V and 0 to +20V.
Data is available in parallel and serial form with
corresponding clock and status output. All digital in-
puts and outputs are TTL-compatible.
Power supply voltages are ±15VDC and +5VDC.
Parallel
Digital
Output
Short Cycle
Convert Command
16-Bit
Successive Approx.
Register (SAR)
16-Bit D/A
Converter
Reference
Ref Out (+6.3V)
}Input Range
Select
Comparator In
Clock
Clock Out
Status
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1990 Burr-Brown Corporation
PDS-1060A
Printed in U.S.A. December, 1993
1 page  
TYPICAL PERFORMANCE CURVES
At +25°C and rated power supplies unless otherwise noted.
+0.10
GAIN DRIFT ERROR (% OF FSR)
vs TEMPERATURE
+0.08
+0.06
+0.04
ADC71AG, BG
ADC71JG,KG
+0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–25°C
0°C +25°C
+70°C +85°C
Temperature (°C)
DISCUSSION OF
PERFORMANCE
The accuracy of a successive approximation A/D converter
is described by the transfer function shown in Figure 1. All
successive approximation A/D converters have an inherent
Quantization Error of ±1/2 LSB. The remaining errors in the
A/D converter are combinations of analog errors due to the
linear circuitry, matching and tracking properties of the
ladder and scaling networks, power supply rejection, and
reference errors. In summary, these errors consist of initial
errors including Gain, Offset, Linearity, Differential Linear-
ity, and Power Supply Sensitivity. Initial Gain and Offset
errors may be adjusted to zero. Gain drift over temperature
rotates the line (Figure 1) about the zero or minus full scale
point (all bits Off) and Offset drift shifts the line left or right
over the operating temperature range. Linearity error is
unadjustable and is the most meaningful indicator of A/D
0000 ... 0000
0000 ... 0001
0111 ... 1101
0111 ... 1110
0111 ... 1111
1000 ... 0000
1000 ... 0001
1111 ... 1110
1111 ... 1111
–1/2LSB
Offset
Error
All Bits Off
All Bits On
Gain
Error
+1/2LSB
eIN On
–FSR/2
Analog Input +FSR/2–1LSB
eIN Off
NOTE: (1) See Table I for Digital Code Definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar A/ D
Converter.
0.1
0.06
0.04
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
–15VDC
0.02
0.01
0.006
0.004
+15VDC
0.002
+5VDC
0.001
NOTE: Pages 4&51 10 100 1k
Frequency (Hz)
were switched for
Abridged Version
for '96 data book.
10k
100k
converter accuracy. Linearity error is the deviation of an
actual bit transition from the ideal transition value at any
level over the range of the A/D converter. A Differential
Linearity error of ±1/2 LSB means that the width of each bit
step over the range of the A/D converter is 1 LSB, ±1/2 LSB.
The ADC71 is monotonic, assuring that the output digital
code either increases or remains the same for increasing
analog input signals. Burr-Brown guarantees that these con-
verters will have no missing codes over a specified tempera-
ture range when short-cycled for 14-bit operation.
TIMING CONSIDERATIONS
The timing diagram (Figure 2) assumes an analog input such
that the positive true digital word 1001 1000 1001 0110
exists. The output will be complementary as shown in Figure
2 (0110 0111 0110 1001 is the digital output). Figures 3 and
4 are timing diagrams showing the relationship of serial data
to clock and valid data to status.
DEFINITION OF DIGITAL CODES
Parallel Data
Two binary codes are available on the ADC71 parallel
output; they are complementary (logic “0” is true) straight
binary (CSB) for unipolar input signal ranges and comple-
mentary offset binary (COB) for bipolar input signal ranges.
Complementary two’s complement (CTC) may be obtained
by inverting MSB (Pin 1).
Table I shows the LSB, transition values, and code defini-
tions for each possible analog input signal range for 12-, 13-
and 14-bit resolutions. Figure 5 shows the connections for
14-bit resolution, parallel data output, with ±10V input.
®
5 ADC71
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ADC71KG.PDF ] | |
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